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1. 发明申请

WO1995032599A2 NON-BLOCKING SWITCHING NETWORK 审中-公开
标题翻译：非阻塞开关网络
公开(公告)号：WO1995032599A2
公开(公告)日：1995-11-30
申请号：PCT/FI1995000288
申请日：1995-05-24
申请人： NOKIA TELECOMMUNICATIONS OY , AHOLA, Reijo , KASURINEN, Timo , KELLOCK, Hamish , SILLANPÄÄ, Tero , URALA, Reino , VIITANEN, Esa , WAINIO, Pekka
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04Q11/06
CPC分类号： H04L49/1553 , H04J2203/0012 , H04J2203/0041 , H04L2012/561 , H04Q11/0478 , H04Q11/06 , H04Q2213/1334
摘要： The invention discloses a cross connect architecture for SDH signals, in which the input stage is composed of parallel TS switch blocks (TSW-SSW), the centre stage (MSW) is composed of parallel time and space switch blocks (STS; TxT-S) and the output stage is a symmetrical mirror image of the input stage. It is advantageous that the centre stage have a large number of blocks (MSW) relative to the minimum need, even double as many, whereby in practice a non-blocking switching network is obtained. All the switch blocks have doubled control memories, which ensure interference-free reconnections.
摘要翻译：本发明公开了一种用于SDH信号的交叉连接架构，其中输入级由并行TS交换块（TSW-SSW）组成，中心级（MSW）由并行时间和空间交换块（STS; TxT-S ），输出级是输入级的对称镜像。有利的是，中心级具有相对于最小需求的大量块（MSW），甚至是双倍数，从而在实践中获得非阻塞交换网络。所有的开关块都具有双倍的控制存储器，确保无干扰的重新连接。

2. 发明申请

WO9532599A3 NON-BLOCKING SWITCHING NETWORK 审中-公开
标题翻译：非阻塞开关网络
公开(公告)号：WO9532599A3
公开(公告)日：1995-12-28
申请号：PCT/FI9500288
申请日：1995-05-24
申请人： NOKIA TELECOMMUNICATIONS OY , AHOLA REIJO , KASURINEN TIMO , KELLOCK HAMISH , SILLANPAEAE TERO , URALA REINO , VIITANEN ESA , WAINIO PEKKA
发明人： AHOLA REIJO , KASURINEN TIMO , KELLOCK HAMISH , SILLANPAEAE TERO , URALA REINO , VIITANEN ESA , WAINIO PEKKA
IPC分类号： H04L12/70 , H04L12/933 , H04Q11/04 , H04Q11/06
CPC分类号： H04L49/1553 , H04J2203/0012 , H04J2203/0041 , H04L2012/561 , H04Q11/0478 , H04Q11/06 , H04Q2213/1334
摘要： The invention discloses a cross connect architecture for SDH signals, in which the input stage is composed of parallel TS switch blocks (TSW-SSW), the centre stage (MSW) is composed of parallel time and space switch blocks (STS; TxT-S) and the output stage is a symmetrical mirror image of the input stage. It is advantageous that the centre stage have a large number of blocks (MSW) relative to the minimum need, even double as many, whereby in practice a non-blocking switching network is obtained. All the switch blocks have doubled control memories, which ensure interference-free reconnections.

3. 发明申请

WO1993016536A1 DESYNCHRONIZER AND METHOD FOR SUPPRESSING POINTER JITTER IN A DESYNCHRONIZER 审中-公开
标题翻译：用于抑制点火器在脱硫剂中的脱乙烷和方法
公开(公告)号：WO1993016536A1
公开(公告)日：1993-08-19
申请号：PCT/FI1993000046
申请日：1993-02-12
申请人： NOKIA TELECOMMUNICATIONS OY , URALA, Reino
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04J3/076 , H04J2203/0089 , H04Q11/0478
摘要： The invention relates to a method for suppressing pointer phase jitter in a desynchronizer comprising a data buffer means (1); a write address counter (2) controlled by a write clock (CLK1); a read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop (4, 5, 7) for phase-locking the read clock to the write clock. The method according to the invention comprises modulating (61, 64) the pointer phase jitter to a frequency substantially higher than the bandwidth of the phase-locked loop.
摘要翻译：本发明涉及一种用于抑制包括数据缓冲器装置（1）的去同步器中的指针相位抖动的方法。由写入时钟（CLK1）控制的写入地址计数器（2）; 由读时钟（CLK2）控制的读地址计数器（3）; 以及用于将读时钟相位锁定到写时钟的锁相环（4,5,7）。根据本发明的方法包括将指针相位抖动（61,64）调制到明显高于锁相环带宽的频率。

4. 发明申请

WO1993016535A1 POINTER JITTER SUPPRESSION IN A DESYNCHRONIZER 审中-公开
标题翻译：点火枪抑制剂在脱硫剂中的作用
公开(公告)号：WO1993016535A1
公开(公告)日：1993-08-19
申请号：PCT/FI1993000045
申请日：1993-02-12
申请人： NOKIA TELECOMMUNICATIONS OY , URALA, Reino
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04Q11/0478 , H04J3/076 , H04J2203/0089
摘要： The invention relates to an arrangement for suppressing pointer justification jitter in a desynchronizer in a digital transmission system, the desynchronizer comprising a data buffer (1); a data buffer write address counter (2) controlled by a write clock (CLK1); a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator (4), a loop filter (A1) and a voltage-controlled oscillator (5) for adjusting said read clock on the basis of the phase difference between the read and write clocks. According to the invention, the arrangement comprises means (A2, 71, 81) for positively controlling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal (DATA OUT) of the desynchronizer by said pointer justification.
摘要翻译：本发明涉及一种用于抑制数字传输系统中的去同步器中的指针对齐抖动的装置，所述去同步器包括数据缓冲器（1）; 由写入时钟（CLK1）控制的数据缓冲器写入地址计数器（2）; 由读时钟（CLK2）控制的数据缓冲器读地址计数器（3）; 以及包括相位比较器（4），环路滤波器（A1）和压控振荡器（5）的锁相环，用于根据读和写时钟之间的相位差来调整所述读时钟。根据本发明，该装置包括用于积极地控制锁相环的装置（A2,71,81），以便与每个指针对齐的发生时间同步地限制相位抖动引起的最大幅度通过所述指针对齐的去同步器的输出信号（DATA OUT）。

5. 发明申请

WO9831117A3 METHOD FOR ATTENUATING TRANSIENTS CAUSED BY ALIGNING IN A DESYNCHRONIZER 审中-公开
标题翻译：用于在脱乙酰化剂中抑制转化引起的瞬态的方法
公开(公告)号：WO9831117A3
公开(公告)日：1998-09-11
申请号：PCT/FI9700788
申请日：1997-12-16
申请人： NOKIA TELECOMMUNICATIONS OY , URALA REINO
发明人： URALA REINO
IPC分类号： H03L7/093 , H04J3/07 , H04J3/06
CPC分类号： H04J3/076 , H03L7/093
摘要： The invention relates to a method to attenuate transients caused in the desynchroniser by justification events in a digital transmission system. The analogue circuit arrangement realising the method comprises a by-pass input for receiving the three-state signal (BPin), whereby the signal (BPin) represents justification events upwards and/or downwards, filtering means (R8 and C8) for filtering the pulse signal (BPin), and adding means (AMP2) for adding the filtered pulse signal to the output signal of the loop filter (AMP1), whereby the added output signal controls the loop oscillator (VCO).

6. 发明申请

WO1998031117A2 METHOD FOR ATTENUATING TRANSIENTS CAUSED BY ALIGNING IN A DESYNCHRONIZER 审中-公开
标题翻译：通过在脱乙酰化剂中对抗引起的瞬态衰减的方法
公开(公告)号：WO1998031117A2
公开(公告)日：1998-07-16
申请号：PCT/FI1997000788
申请日：1997-12-16
申请人： NOKIA TELECOMMUNICATIONS OY , URALA, Reino
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04J3/076 , H03L7/093
摘要： The invention relates to a method to attenuate transients caused in the desynchroniser by justification events in a digital transmission system. The analogue circuit arrangement realising the method comprises a by-pass input for receiving the three-state signal (BPin), whereby the signal (BPin) represents justification events upwards and/or downwards, filtering means (R8 and C8) for filtering the pulse signal (BPin), and adding means (AMP2) for adding the filtered pulse signal to the output signal of the loop filter (AMP1), whereby the added output signal controls the loop oscillator (VCO).
摘要翻译：本发明涉及通过数字传输系统中的调整事件来衰减在失步器中引起的瞬变的方法。实现该方法的模拟电路装置包括用于接收三态信号（BPin）的旁路输入，由此信号（BPin）表示向上和/或向下的调整事件，用于滤波脉冲的滤波装置（R8和C8）信号（BPin）和用于将滤波的脉冲信号加到环路滤波器（AMP1）的输出信号的加法装置（AMP2），由此所加的输出信号控制环路振荡器（VCO）。

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