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1. 发明申请

WO2008067642A1 APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 审中-公开
标题翻译：用于生产混合类型的串联互连设备的设备标识符的装置和方法
公开(公告)号：WO2008067642A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002147
申请日：2007-11-29
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , SUMI, Shuji , KIM, Jin-Ki
发明人： PYEON, Hong Beom , OH, HakJune , SUMI, Shuji , KIM, Jin-Ki
IPC分类号： G11C8/06 , G11C16/20 , G11C8/12
CPC分类号： G11C16/20 , G11C8/12
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (Sl) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a "don't care" code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。每个设备都有其设备类型的设备类型信息。包含在串行输入（S1）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。在将不同的设备类型分别提供给互连设备的情况下，在不同设备类型的每一种中生成顺序ID，并且还识别每种设备类型的总数。在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异如何。

2. 发明申请

WO2008067650A1 APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 审中-公开
标题翻译：用于生产混合类型的串联互连设备的设备标识符的装置和方法
公开(公告)号：WO2008067650A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002171
申请日：2007-12-04
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki , SUMI, Shuji
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki , SUMI, Shuji
IPC分类号： G11C8/18 , G06F12/00 , G06F7/48 , G11C19/00 , G11C8/12
CPC分类号： G06F12/0676 , G06F13/1694 , G11C5/147
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

3. 发明申请

WO2008067665A1 APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION 审中-公开
标题翻译：用于生产符合串行互连的混合器件类型的标识符的装置和方法
公开(公告)号：WO2008067665A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002193
申请日：2007-12-04
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki , SUMI, Shuji
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki , SUMI, Shuji
IPC分类号： G11C19/00 , G06F12/00 , G11C7/10 , G11C8/12 , H03M9/00
CPC分类号： G06F12/0684 , G06F12/0661 , G11C8/12 , G11C8/20
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. A memory controller can recognize the total number of one DT, in response to the ID received from the last device. In a case of a "don't care" DT is provided to the interconnected devices, IDs are sequentially generated and the total number of the interconnected devices is recognized, regardless of the differences in DTs of the devices.
摘要翻译：混合型的多个存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。响应于从最后一个设备接收的ID，存储器控制器可以识别一个DT的总数。在“不关心”的情况下，将DT提供给互连设备，不管设备的DT的差异如何，顺序地生成ID并且识别互连设备的总数。

4. 发明申请

WO2008101317A1 APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA 审中-公开
标题翻译：用于具有镜像备份数据的存储器件的页面程序操作的装置和方法
公开(公告)号：WO2008101317A1
公开(公告)日：2008-08-28
申请号：PCT/CA2008/000273
申请日：2008-02-13
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C7/24 , G11C19/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
摘要翻译：提供了一种页面编程操作的装置和方法。当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本。在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

5. 发明申请

WO2008067658A1 SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE 审中-公开
标题翻译：混合型记忆装置的操作系统及方法
公开(公告)号：WO2008067658A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002182
申请日：2007-12-04
申请人： MOSAID TECHNOLOGIES INCORPORATED , OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
发明人： OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
IPC分类号： G11C8/18 , G06F12/00 , G11C11/34 , G11C16/02 , G11C8/04 , G11C8/06
CPC分类号： G11C16/08 , G11C7/10 , G11C7/1078 , G11C7/20
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

6. 发明申请

WO2008101318A1 SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的页面缓冲器操作的系统和方法
公开(公告)号：WO2008101318A1
公开(公告)日：2008-08-28
申请号：PCT/CA2008/000287
申请日：2008-02-15
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , KIM, Jin-Ki , OH, HakJune
发明人： PYEON, Hong Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C7/10 , G06F12/00 , G11C16/02
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
摘要翻译：提供了系统和方法，用于使用通过公共总线连接到存储器控制器的存储器件的页缓冲器。使用存储器件的页缓冲器作为写入存储器件的存储单元的数据的临时高速缓存。这可以允许内存控制器使用内存设备作为临时缓存，以便内存控制器可以释放自己内存中的空间。

7. 发明申请

WO2008022454A1 SCALABLE MEMORY SYSTEM 审中-公开
标题翻译：可扩展存储系统
公开(公告)号：WO2008022454A1
公开(公告)日：2008-02-28
申请号：PCT/CA2007/001469
申请日：2007-08-22
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki , OH, HakJune , PYEON, Hong Beom , PRZYBYLSKI, Steven
发明人： KIM, Jin-Ki , OH, HakJune , PYEON, Hong Beom , PRZYBYLSKI, Steven
IPC分类号： G11C7/10 , G11C5/14 , G11C8/18
CPC分类号： G11C7/1042 , G11C7/10 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C8/04 , G11C16/0483
摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
摘要翻译：存储器系统架构具有串行连接的存储器件。内存系统是可扩展的，可以包括任何数量的内存设备，而不会造成任何性能下降或重新设计。每个存储器件具有用于在其他存储器件和存储器控制器之间通信的串行输入/输出接口。存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

8. 发明申请

WO2008098342A1 SEMICONDUCTOR DEVICE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYSTEM HAVING INTERCONNECTED DEVICES 审中-公开
标题翻译：用于降低具有互连装置的系统中的功率消耗的半导体装置和方法
公开(公告)号：WO2008098342A1
公开(公告)日：2008-08-21
申请号：PCT/CA2008/000120
申请日：2008-01-23
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C5/14 , G11C19/00 , G11C8/12
CPC分类号： G11C19/00
摘要： A system includes a plurality of memory devices connected in-series that communicate with a memory controller. A memory device designated by an ID number performs operations at a normal power consumption level. The other devices not designated perform signal forwarding operations at a reduced power consumption level. The designated memory device enables its internal clock generator to generate all clocks necessary for operations. The non-designated memory devices generate clocks to perform partial operations for forwarding commands to next memory devices. In another example, memory devices do not forward the input command to the next memory device when there is no ID match. In another example, a memory device transmits the command replacing the content thereof with a static output when there is an ID match. Such partial clock generation, non-forwarding of commands and replacing the command contents will cause the system to operate at the reduced power consumption level.
摘要翻译：系统包括与存储器控制器通信的串联连接的多个存储器件。由ID号码指定的存储器件以正常功耗水平进行操作。未指定的其他设备以降低的功耗水平执行信号转发操作。指定的存储器件使其内部时钟发生器能够生成操作所需的所有时钟。非指定存储器件产生时钟以执行用于将命令转发到下一个存储器件的部分操作。在另一个示例中，当没有ID匹配时，存储器件不将输入命令转发到下一个存储器件。在另一示例中，当存在ID匹配时，存储装置传送替换其内容的命令与静态输出。这种部分时钟产生，不转发命令和替换命令内容将导致系统以降低的功耗水平操作。

9. 发明申请

WO2008067652A1 ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE 审中-公开
标题翻译：混合类型的串联互连存储器件的地址分配和类型识别
公开(公告)号：WO2008067652A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002173
申请日：2007-12-04
申请人： MOSAID TECHNOLOGIES INCORPORATED , OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
发明人： OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
IPC分类号： G11C19/00 , G06F12/00 , G11C7/10 , G11C7/22 , G11C8/12 , G11C8/18 , H03M9/00
CPC分类号： G11C7/20 , G06F12/0653 , G06F13/1694 , G11C7/10 , G11C8/12 , G11C8/18
摘要： A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.
摘要翻译：提供了存储器系统架构，其中存储器控制器控制串行互连配置中的存储器件的操作。存储器控制器具有用于发送存储器命令的输出串行接口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入串行接口。每个存储器件包括存储器，例如闪速存储器（例如NAND和NOR型闪速存储器）。在初始化阶段，存储器设备被分配有连续的地址。存储器控制器发送目标地址并且可以识别目标存储器件的类型。存储器命令和存储器响应的数据路径由互连提供。

10. 发明申请

WO2007134444A1 APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
标题翻译：用于建立串行互连设备的设备标识符的装置和方法
公开(公告)号：WO2007134444A1
公开(公告)日：2007-11-29
申请号：PCT/CA2007/000891
申请日：2007-05-18
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4256 , G06F2213/0052
摘要： A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.
摘要翻译：一种方法或设备操作串行互连配置中的多个设备以建立每个设备的设备标识符（ID）。输入信号通过使用也由第一装置用于输入其它信息（例如，数据，命令，控制信号）的输入通过串行互连传输到第一装置。发生电路响应于输入信号产生设备ID。传输电路然后通过第一设备的串行输出将与设备ID相关联的输出信号传送到第二设备。串行输出也被第一设备用于在串行互连配置中向另一设备输出其他信息（例如，信号，数据）。

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