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1. 发明申请

WO2010096153A3 DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS 审中-公开
标题翻译：内存控制器和方法中的数据完整性
公开(公告)号：WO2010096153A3
公开(公告)日：2010-11-25
申请号：PCT/US2010000412
申请日：2010-02-12
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , YAMADA RONALD , NEMAZIE SIAMACK , YANG RAY
发明人： ASNAASHARI MEHDI , YAMADA RONALD , NEMAZIE SIAMACK , YANG RAY
IPC分类号： G06F11/08 , G06F9/06 , G06F13/16
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1004 , G06F13/28 , G06F21/64 , G11C2029/0411 , H03M13/09 , H03M13/13 , H03M13/29
摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
摘要翻译：本公开包括用于存储器控制器中的数据完整性的方法，设备和系统。一个存储器控制器实施例包括耦合到主机接口的主机接口和第一错误检测电路。存储器控制器可以包括耦合到存储器接口的存储器接口和第二错误检测电路。第一错误检测电路可以被配置为计算从主机接口接收的数据的错误检测数据，并检查发送到主机接口的数据的完整性。第二错误检测电路可以被配置为计算发送到存储器接口的数据和第一纠错数据的纠错数据，并且检查数据的完整性和从存储器接口接收到的第一纠错数据。

2. 发明申请

WO2010117404A3 MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVERS AND METHODS FOR PROCESSING A NUMBER OF COMMANDS 审中-公开
标题翻译：存储器控制器，存储器系统，固态驱动器和处理多个命令的方法
公开(公告)号：WO2010117404A3
公开(公告)日：2011-03-31
申请号：PCT/US2010000732
申请日：2010-03-11
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , LIAO YU-SONG , YANG RAY , NEMAZIE SIAMACK
发明人： ASNAASHARI MEHDI , LIAO YU-SONG , YANG RAY , NEMAZIE SIAMACK
IPC分类号： G06F13/16 , G06F3/06 , G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译：本公开包括用于存储器控制器的方法和装置。在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。命令队列配置为保存从主机接收的主机命令。电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。

3. 发明申请

WO2010101609A3 MEMORY BLOCK MANAGEMENT 审中-公开
标题翻译：存储器块管理
公开(公告)号：WO2010101609A3
公开(公告)日：2010-11-25
申请号：PCT/US2010000540
申请日：2010-02-24
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK
发明人： ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译：各种实施例包括一个或多个具有被组织成超级块的物理块的至少两个平面的存储器设备，每个超级块包括来自至少两个平面中的每一个的物理块。实施例包括确定平面内的缺陷块。如果确定特定块位置处的块都不存在缺陷，则实施例包括将特定块位置处的块分配给超级块，并且如果特定块位置处的一个或多个块被确定为有缺陷，实施例包括：将被确定为有缺陷的特定块位置处的块分配给超级块; 以及针对被确定为有缺陷的特定块位置处的一个或多个块中的每一个块，将相应的替换块分配给超块。相应的替换块从包括被确定为有缺陷的相应块的相应的一个平面内的多个块中选择。

4. 发明申请

WO2010101608A3 MEMORY BLOCK SELECTION 审中-公开
标题翻译：存储器块选择
公开(公告)号：WO2010101608A3
公开(公告)日：2010-11-25
申请号：PCT/US2010000539
申请日：2010-02-24
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK , MCNAMARA DALE P
发明人： ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK , MCNAMARA DALE P
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7204 , G06F2212/7205 , G06F2212/7208
摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.
摘要翻译：本公开包括用于存储器块选择的方法和设备。在一个或多个实施例中，存储器控制器包括耦合到一个或多个存储器设备的控制电路，该存储器设备具有与其相关联的多组平面，每个组包括被组织成超级块的至少两个物理块平面，每个超级块包括物理块来自至少两个平面中的每一个。控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并确定多个组中选定的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

5. 发明申请

WO2009064621A2 SMART STORAGE DEVICE 审中-公开
标题翻译：智能存储设备
公开(公告)号：WO2009064621A2
公开(公告)日：2009-05-22
申请号：PCT/US2008081913
申请日：2008-10-31
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , TSAI VICTOR
发明人： ASNAASHARI MEHDI , TSAI VICTOR
IPC分类号： G06K19/073 , G06F15/00 , G06K19/10
CPC分类号： G06F12/1408 , G06F21/602 , G06F21/77 , G06F21/79 , G06F2212/1052 , H04L9/0897 , H04L9/3226
摘要： A smart storage device (200) can have a smart-card portion (205) with access control circuitry and integrated memory, a controller (210) in selective communication with the smart-card portion (205), and a memory device (250) in communication with the controller (210). The memory device (250) can be separate from the smart-card portion (205) and can store one or more smart-card applications (260).
摘要翻译：智能存储设备（200）可以具有带有访问控制电路和集成存储器的智能卡部分（205），与智能卡部分（205）选择性地通信的控制器（210）和存储器设备（250）与控制器（210）通信。存储器件（250）可以与智能卡部分（205）分离，并且可以存储一个或多个智能卡应用（260）。

6. 发明申请

WO2009064634A3 SYSTEM AND METHOD FOR UPDATING READ-ONLY MEMORY IN SMART CARD MEMORY MODULES 审中-公开
标题翻译：用于在智能卡存储器模块中更新只读存储器的系统和方法
公开(公告)号：WO2009064634A3
公开(公告)日：2009-07-23
申请号：PCT/US2008082312
申请日：2008-11-04
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , SHAH RUCHIRKUMAR D , PREVOST SYLVAIN , KRISHNA KSHEERABDHI
发明人： ASNAASHARI MEHDI , SHAH RUCHIRKUMAR D , PREVOST SYLVAIN , KRISHNA KSHEERABDHI
IPC分类号： G06K19/07 , G06F9/44
CPC分类号： H04L9/0877 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06F12/0238 , G06F12/1425 , G06F21/79 , G06F2206/1014 , H04L9/0863 , H04L9/3234
摘要： A storage device contains smart-card device and memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from "read-only" to "read/write" to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.
摘要翻译：存储设备包含连接到控制器的智能卡设备和存储设备。存储装置可以以与常规智能卡装置相同的方式使用，或者可以用于将相对大量的数据存储在各个分区中。这些分区中的一个可以是只读分区通常只能访问的只读分区。然而，有时可能需要更新或补充存储在只读分区中的数据。这通过主机向存储设备发出适当的命令来实现，该命令可以伴随有适当级别的授权的标识符。然后，控制器将只读分区的属性从“只读”更改为“读/写”，以允许将数据写入分区。完成后，控制器将分区的属性更改回只读。

7. 发明申请

WO2008127408A2 METHOD AND SYSTEM FOR ENCRYPTION OF INFORMATION STORED IN AN EXTERNAL NONVOLATILE MEMORY 审中-公开
标题翻译：用于加密存储在外部非易失性存储器中的信息的方法和系统
公开(公告)号：WO2008127408A2
公开(公告)日：2008-10-23
申请号：PCT/US2007083763
申请日：2007-11-06
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI
发明人： ASNAASHARI MEHDI
CPC分类号： G06F21/80 , G06F21/79
摘要： A nonvolatile storage system is described that includes a controller for transferring information between a host and nonvolatile memory. The controller includes an encryption/decryption engine for transferring information to and from a nonvolatile memory device, located externally to the controller, using a first key to encrypt information being stored into the nonvolatile memory device prior to storage thereof and further using the first key to decrypt the stored encrypted information after retrieval of thereof. Alternatively, a second key is used in conjunction with the first key to add further security to the information stored within the nonvolatile memory.
摘要翻译：描述了一种非易失性存储系统，其包括用于在主机和非易失性存储器之间传送信息的控制器。该控制器包括一个加密/解密引擎，用于使用第一密钥在存储之前将存储在非易失性存储器件中的信息加密，并且进一步使用第一密钥将信息传送到来自位于控制器外部的非易失性存储器件的信息在检索之后对存储的加密信息进行解密。或者，第二密钥与第一密钥结合使用，以便为存储在非易失性存储器中的信息增加进一步的安全性。

8. 发明申请

WO2010090696A3 LOGICAL ADDRESS OFFSET 审中-公开
标题翻译：逻辑地址偏差
公开(公告)号：WO2010090696A3
公开(公告)日：2010-10-21
申请号：PCT/US2010000095
申请日：2010-01-15
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , BENSON WILLIAM E
发明人： ASNAASHARI MEHDI , BENSON WILLIAM E
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F3/0608 , G06F3/0638 , G06F3/0679 , G06F12/0246 , G06F2212/7202
摘要： The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
摘要翻译：本公开包括用于逻辑地址偏移的方法，设备和系统。一种方法实施例包括检测存储器单元格式化操作。随后，响应于检测格式化操作，该方法包括检查存储器单元上的格式信息，计算逻辑地址偏移量，以及将偏移量应用于主机逻辑地址。

9. 发明申请

WO2009064631A3 CRITICAL SECURITY PARAMETER GENERATION AND EXCHANGE SYSTEM AND METHOD FOR SMART-CARD MEMORY MODULES 审中-公开
标题翻译：智能卡记忆模块的关键安全参数生成和交换系统及方法
公开(公告)号：WO2009064631A3
公开(公告)日：2009-07-02
申请号：PCT/US2008082259
申请日：2008-11-03
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , SHAH RUCHIRKUMAR D , PREVOSE SYLVAIN , KRISHNA KSHEERABDHI
发明人： ASNAASHARI MEHDI , SHAH RUCHIRKUMAR D , PREVOSE SYLVAIN , KRISHNA KSHEERABDHI
IPC分类号： G06K19/073 , G06F12/14 , G06F21/00
CPC分类号： H04L9/3234 , G06F21/34 , G06F21/77 , G06F21/79 , G06Q20/3563
摘要： A storage device contains a smart-card device and memory device, which is connected to a controller. The storage device may be used in the same manner as conventional smart-card device, or it may be used to store relatively large amount of data. The memory device may also be used to store data or instructions for use by smart-card device. The controller includes a security engine that uses critical security parameters stored in, and received from, the smart-card device. The critical security parameters may be sent to the controller in a manner that protects them from being discovered. The critical security parameters may be encryption and/or decryption keys that may encrypt data written to the memory device and/or decrypt data read from the memory device, respectively. Data and instructions used by the smart-card device may therefore stored in the memory device in encrypted form.
摘要翻译：存储设备包含连接到控制器的智能卡设备和存储设备。存储装置可以以与常规智能卡装置相同的方式使用，或者可以用于存储相对大量的数据。存储器件还可用于存储智能卡设备使用的数据或指令。控制器包括使用存储在智能卡设备中并从智能卡设备接收的关键安全参数的安全引擎。关键的安全参数可以以保护它们免受发现的方式发送到控制器。关键的安全参数可以是加密和/或解密密钥，其可分别加密写入存储器件的数据和/或解密从存储器件读取的数据。因此，智能卡设备使用的数据和指令可以以加密形式存储在存储设备中。

10. 发明申请

WO2010033375A3 SATA MASS STORAGE DEVICE EMULATION ON A PCIE INTERFACE 审中-公开
标题翻译： SATA大容量存储设备在PCIE接口上的仿真
公开(公告)号：WO2010033375A3
公开(公告)日：2010-05-27
申请号：PCT/US2009055652
申请日：2009-09-02
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI
发明人： ASNAASHARI MEHDI
IPC分类号： G06F13/14 , G06F3/06 , G06F13/38
CPC分类号： G06F13/385 , G06F2213/3802
摘要： A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA mass storage device over a PCIe interface with a host system. The host system generates commands with the PCIe mass storage device in the same format as if communicating with a SATA mass storage device. The PCIe mass storage device responds in the same SATA format.
摘要翻译：公开了一种用于操作大容量存储装置的大容量存储装置，系统和方法。在一个这样的大容量存储设备中，主机总线适配器通过与主机系统的PCIe接口模拟SATA大容量存储设备。主机系统以与大容量存储设备通信相同的格式与PCIe大容量存储设备一起生成命令。 PCIe大容量存储设备以相同的SATA格式进行响应。

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