专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010101609A3 MEMORY BLOCK MANAGEMENT 审中-公开
标题翻译：存储器块管理
公开(公告)号：WO2010101609A3
公开(公告)日：2010-11-25
申请号：PCT/US2010000540
申请日：2010-02-24
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK
发明人： ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译：各种实施例包括一个或多个具有被组织成超级块的物理块的至少两个平面的存储器设备，每个超级块包括来自至少两个平面中的每一个的物理块。实施例包括确定平面内的缺陷块。如果确定特定块位置处的块都不存在缺陷，则实施例包括将特定块位置处的块分配给超级块，并且如果特定块位置处的一个或多个块被确定为有缺陷，实施例包括：将被确定为有缺陷的特定块位置处的块分配给超级块; 以及针对被确定为有缺陷的特定块位置处的一个或多个块中的每一个块，将相应的替换块分配给超块。相应的替换块从包括被确定为有缺陷的相应块的相应的一个平面内的多个块中选择。

2. 发明申请

WO2010101608A3 MEMORY BLOCK SELECTION 审中-公开
标题翻译：存储器块选择
公开(公告)号：WO2010101608A3
公开(公告)日：2010-11-25
申请号：PCT/US2010000539
申请日：2010-02-24
申请人： MICRON TECHNOLOGY INC , ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK , MCNAMARA DALE P
发明人： ASNAASHARI MEHDI , CHEN ALAN , NEMAZIE SIAMACK , MCNAMARA DALE P
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7204 , G06F2212/7205 , G06F2212/7208
摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.
摘要翻译：本公开包括用于存储器块选择的方法和设备。在一个或多个实施例中，存储器控制器包括耦合到一个或多个存储器设备的控制电路，该存储器设备具有与其相关联的多组平面，每个组包括被组织成超级块的至少两个物理块平面，每个超级块包括物理块来自至少两个平面中的每一个。控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并确定多个组中选定的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

3. 发明申请

WO2010101608A2 MEMORY BLOCK SELECTION 审中-公开
标题翻译：内存块选择
公开(公告)号：WO2010101608A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/000539
申请日：2010-02-24
申请人： MICRON TECHNOLOGY, INC. , ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack , MCNAMARA, Dale, P.
发明人： ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack , MCNAMARA, Dale, P.
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7204 , G06F2212/7205 , G06F2212/7208
摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.
摘要翻译：本公开包括用于存储块选择的方法和装置。在一个或多个实施例中，存储器控制器包括耦合到具有与其相关联的多组平面的一个或多个存储器件的控制电路，每个组包括组织成超级块的至少两个物理块平面，每个超级块包括物理块从至少两个平面的每一个。控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并且确定多个组中所选择的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

4. 发明申请

WO2007008325A2 MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS 审中-公开
标题翻译：具有高级主位分割电路的增强型擦除/程序/验证操作的存储器架构
公开(公告)号：WO2007008325A2
公开(公告)日：2007-01-18
申请号：PCT/US2006022946
申请日：2006-06-13
申请人： ATMEL CORP , HONG STANLEY , WANG JAMI , CHEN ALAN
发明人： HONG STANLEY , WANG JAMI , CHEN ALAN
IPC分类号： G11C8/00
CPC分类号： G11C16/24 , G11C7/12 , G11C7/18 , G11C16/3445 , G11C16/3459 , G11C2207/002
摘要： The present invention provides a solution for long master bit lines (180a-180c) in a large capacity memory device (100) . A master bit line is partitioned by at least one switching transistor (181a-181i) placed on the master bit line.
摘要翻译：本发明提供了一种用于大容量存储器件（100）中的长主位线（180a-180c）的解决方案。主位线被放置在主位线上的至少一个开关晶体管（181a-181i）分隔。

5. 发明申请

WO2008100312A1 METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A CMOS FLOW 审中-公开
标题翻译：降低双极晶体管的集电极电阻并集成到CMOS流中的方法
公开(公告)号：WO2008100312A1
公开(公告)日：2008-08-21
申请号：PCT/US2007/062100
申请日：2007-02-14
申请人： AGERE SYSTEMS, INC. , CHEN, Alan, S. , DYSON, Mark , ROSSI, Nace, M. , SINGH, Ranbir , YUAN, Xiaojun
发明人： CHEN, Alan, S. , DYSON, Mark , ROSSI, Nace, M. , SINGH, Ranbir , YUAN, Xiaojun
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249
摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
摘要翻译：本发明在一个方面提供一种用于制造半导体器件的方法。在一个方面，该方法提供双注入双极晶体管的桶。通过将单独的注入掩模注入到双极区域中，通过在MOS晶体管的制造期间也用于植入与在非双极区域中制造不同电压器件的MOS相关联的管道的桶。

6. 发明申请

WO2010101609A2 MEMORY BLOCK MANAGEMENT 审中-公开
标题翻译：内存块管理
公开(公告)号：WO2010101609A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/000540
申请日：2010-02-24
申请人： MICRON TECHNOLOGY, INC. , ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack
发明人： ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译：各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。实施例包括确定平面内的有缺陷的块。如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷，实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。

7. 发明申请

WO2010040131A2 VESSEL PROTECTION DEVICE 审中-公开
标题翻译：船舶保护装置
公开(公告)号：WO2010040131A2
公开(公告)日：2010-04-08
申请号：PCT/US2009/059559
申请日：2009-10-05
申请人： REPLICATION MEDICAL, INC. , PREWETT, Ann , DINGLEDINE, Mark , CHEN, Alan, C.
发明人： PREWETT, Ann , DINGLEDINE, Mark , CHEN, Alan, C.
IPC分类号： A61L31/10 , A61L31/14
CPC分类号： A61L31/10
摘要： The present disclosure relates to a vessel/tissue protection device having a polymer coated reinforcing layer. The polymer can comprise a biocompatible polymer that will not promote tissue in-growth or attachment, such as segmented polyurethane, polycarbonate urethane, polyether urethane, polyacrylonitrile, etc. The reinforcing layer can comprise any suitable woven, non-woven, knitted, or braided reinforcing polymer, fabric, or foil that is biocompatible and capable of holding a suture, staple, or other attachment device.
摘要翻译：本公开涉及具有聚合物涂覆的增强层的血管/组织保护装置。聚合物可以包含不促进组织生长或附着的生物相容性聚合物，例如分段聚氨酯，聚碳酸酯聚氨酯，聚醚聚氨酯，聚丙烯腈等。增强层可以包括任何合适的织造，无纺布，针织或编织增强聚合物，织物或箔，其是生物相容的并且能够保持缝合线，钉或其它附接装置。

8. 发明申请

WO2007142622A1 BIPOLAR JUNCTION TRANSISTOR WITH A REDUCED COLLECTOR- SUBSTRATE CAPACITANCE 审中-公开
标题翻译：具有减少集电极 - 基板电容的双极晶体管
公开(公告)号：WO2007142622A1
公开(公告)日：2007-12-13
申请号：PCT/US2006/021396
申请日：2006-06-02
申请人： AGERE SYSTEMS INC. , CHEN, Alan, Sangone , DYSON, Mark, Victor , HARRIS, Edward, Belden , KERR, Daniel, Charles , NAGY, William, John
发明人： CHEN, Alan, Sangone , DYSON, Mark, Victor , HARRIS, Edward, Belden , KERR, Daniel, Charles , NAGY, William, John
IPC分类号： H01L29/08 , H01L29/40
CPC分类号： H01L29/0821 , H01L29/404
摘要： A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semiconductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.
摘要翻译：在半导体衬底中形成双极结型晶体管（BJT）的工艺和根据该工艺形成的BJT。在BJT结构之下形成掩埋隔离区，以将BJT结构与p型半导体衬底隔离。为了减小BJT子集电极和掩埋隔离区之间的电容，在植入之前，在基板的表面上形成间接分离结构的子集电极。子集电极通过将离子注入间隔开的结构并通过间隔开的结构之间的区域而形成。因此，形成的BJT子集电极包括主体部分和从其延伸的端部，其端部设置在比主体部分更浅的深度，因为注入端部的离子必须通过间隔开的结构。端部较浅的深度减小了电容。

9. 发明申请

WO2007008325A3 MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS 审中-公开
公开(公告)号：WO2007008325A3
公开(公告)日：2007-01-18
申请号：PCT/US2006/022946
申请日：2006-06-13
申请人： ATMEL CORPORATION , HONG, Stanley , WANG, Jami , CHEN, Alan
发明人： HONG, Stanley , WANG, Jami , CHEN, Alan
IPC分类号： G11C8/00
摘要： The present invention provides a solution for long master bit lines (180a-180c) in a large capacity memory device (100) . A master bit line is partitioned by at least one switching transistor (181a-181i) placed on the master bit line.

10. 发明申请

WO2010040131A3 VESSEL PROTECTION DEVICE 审中-公开
标题翻译：船舶保护装置
公开(公告)号：WO2010040131A3
公开(公告)日：2011-04-21
申请号：PCT/US2009059559
申请日：2009-10-05
申请人： REPLICATION MEDICAL INC , PREWETT ANN , DINGLEDINE MARK , CHEN ALAN C
发明人： PREWETT ANN , DINGLEDINE MARK , CHEN ALAN C
IPC分类号： A61L31/10 , A61L31/14
CPC分类号： A61L31/10
摘要： The present disclosure relates to a vessel/tissue protection device having a polymer coated reinforcing layer. The polymer can comprise a biocompatible polymer that will not promote tissue in-growth or attachment, such as segmented polyurethane, polycarbonate urethane, polyether urethane, polyacrylonitrile, etc. The reinforcing layer can comprise any suitable woven, non-woven, knitted, or braided reinforcing polymer, fabric, or foil that is biocompatible and capable of holding a suture, staple, or other attachment device.
摘要翻译：本公开涉及具有聚合物涂覆的增强层的血管/组织保护装置。聚合物可以包含不促进组织生长或附着的生物相容性聚合物，例如分段聚氨酯，聚碳酸酯聚氨酯，聚醚聚氨酯，聚丙烯腈等。增强层可以包括任何合适的织造，无纺布，针织或编织增强聚合物，织物或箔，其是生物相容的并且能够保持缝合线，钉或其它附接装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式