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1. 发明申请

WO2007067275A2 VLIW ACCELERATION SYSTEM USING MULTI-STATE LOGIC 审中-公开
标题翻译：使用多状态逻辑的VLIW加速系统
公开(公告)号：WO2007067275A2
公开(公告)日：2007-06-14
申请号：PCT/US2006/042499
申请日：2006-10-30
申请人： LIGA SYSTEMS, INC. , COLWILL, Paul , VERHEYEN, Henry, T.
发明人： COLWILL, Paul , VERHEYEN, Henry, T.
IPC分类号： G06F15/00
CPC分类号： G06F9/30145 , G06F17/5022
摘要： A logic simulation processor uses multi-state logic (e.g., in 4-state, signals may take the values 0, 1, X or Z in the simulation of a semiconductor chip design). Typically a reduced number of basic multi-state logic functions are selected for the instruction set of the processor. Logic functions that are not part of the basic set are simulated by constructing them from combinations of the basic logic functions. In this way, the instruction length remains a manageable size but all logic functions that may occur can be simulated. The basic VLIW architecture can be extended to other applications.
摘要翻译：逻辑模拟处理器使用多状态逻辑（例如，在4状态中，在半导体芯片设计的仿真中信号可以取值0,1，X或Z）。通常，为处理器的指令集选择减少数量的基本多状态逻辑功能。不是基本集合的一部分的逻辑功能是通过从基本逻辑功能的组合构成的。以这种方式，指令长度仍然是可管理的大小，但是可以模拟可能发生的所有逻辑功能。基本的VLIW架构可以扩展到其他应用。

2. 发明申请

WO2007121452A2 BRANCHING AND BEHAVIORAL PARTITIONING FOR A VLIW PROCESSOR 审中-公开
标题翻译： VLIW处理器的分支和行为分配
公开(公告)号：WO2007121452A2
公开(公告)日：2007-10-25
申请号：PCT/US2007/066813
申请日：2007-04-17
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , SAHAI, Paraminder, S. , WATT, William , COLWILL, Paul
发明人： VERHEYEN, Henry, T. , SAHAI, Paraminder, S. , WATT, William , COLWILL, Paul
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： In one aspect, the present invention overcomes the limitations of the prior art by providing a logic simulation system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.
摘要翻译：在一个方面，本发明通过提供一种使用具有多个并行处理器元件的VLIW仿真处理器来加速可合成任务的仿真的逻辑仿真系统来克服现有技术的限制，但也支持非可合成任务和/或分支。在一种方法中，VLIW模拟处理器基于不具有片上指令高速缓存的架构。相反，直接从程序存储器和各个处理器元件的VLIW指令字流基于指令字被连续编程。这也允许有效地实施侧入口跳跃，其中可以在区域中间输入代码区域，而不是总是需要从顶部进入。另一方面，非可合成任务可以由异常处理程序有效地处理。

3. 发明申请

WO2007078484A2 PROCESSOR 审中-公开
标题翻译：处理器
公开(公告)号：WO2007078484A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/045771
申请日：2006-11-29
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , MATHUR, Raj, Kumar , WATT, Wiliam
发明人： VERHEYEN, Henry, T. , MATHUR, Raj, Kumar , WATT, Wiliam
IPC分类号： G06F15/00
CPC分类号： G06F15/7832 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor device, a memory device and a circuit board. The circuit board includes a substrate, electrical contacts, and interconnection lines between the contacts. The electrical contacts of the circuit board may be coupled to electrical contacts on the processor device and the memory device. The interconnection lines communicate signals, such as data or instructions, between the electrical contacts of the memory device and the process device at least 200 billion bits per second while related input/output activity of the processor and the memory consumes an average power less than ten watts.
摘要翻译：一种处理器系统，包括具有高数据传输速率和相关I / O活动的低平均功耗的处理器和存储器系统。处理器系统可以设置在单个电路板上。所公开的系统的一个实施例包括处理器系统，其包括处理器装置，存储装置和电路板。电路板包括基板，电触点和触点之间的互连线。电路板的电触点可以耦合到处理器装置和存储装置上的电触点。互连线路在存储器件的电触头和处理器件之间的信号（例如数据或指令）之间传送至少200亿比特/秒，而处理器和存储器的相关输入/输出活动消耗的平均功率小于10 瓦。

4. 发明申请

WO2007037935A2 HARDWARE ACCELERATION SYSTEM FOR LOGIC SIMULATION USING SHIFT REGISTER AS LOCAL CACHE 审中-公开
标题翻译：使用移位寄存器作为本地缓存的逻辑模拟的硬件加速系统
公开(公告)号：WO2007037935A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/034865
申请日：2006-09-07
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , WATT, William
发明人： VERHEYEN, Henry, T. , WATT, William
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units can also include one or more bypass multiplexers coupled between the output of the processor element and the interconnect system, for providing a path for bypassing the shift register to provide the output of the processor element directly to the interconnect system.
摘要翻译：模拟处理器包括多个处理器单元和将处理器单元彼此通信耦合的互连系统。每个处理器单元包括可配置为至少模拟逻辑运算的处理器元件和用于存储在逻辑模拟期间生成的中间值的移位寄存器。每个处理器单元还包括一个或多个复用器，用于选择移位寄存器的条目之一作为要耦合到互连系统的输出。每个处理器单元还可以包括耦合在处理器元件的输出和互连系统之间的一个或多个旁路多路复用器，用于提供用于旁路移位寄存器以将处理器元件的输出直接提供给互连系统的路径。

5. 发明申请

WO2007067399A2 PARTITIONING OF TASKS FOR EXECUTION BY A VLIW HARDWARE ACCELERATION SYSTEM 审中-公开
标题翻译：用于执行VLIW硬件加速系统的任务分配
公开(公告)号：WO2007067399A2
公开(公告)日：2007-06-14
申请号：PCT/US2006/045712
申请日：2006-11-29
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , WATT, William
发明人： VERHEYEN, Henry, T. , WATT, William
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one aspect, logic simulation of a design of a semiconductor chip is performed on a domain-by-domain basis (e.g., by clock domain), but storing a history of the state space of the domain during simulation. In this way, additional information beyond just the end result can be reviewed in order to debug or otherwise analyze the design.
摘要翻译：在一个方面，半导体芯片的设计的逻辑模拟在逐个域（例如，通过时钟域）执行，但是在仿真期间存储域的状态空间的历史。以这种方式，除了最终结果之外的其他信息可以被审查，以便调试或以其他方式分析设计。

6. 发明申请

WO2007064716A2 HARDWARE ACCELERATION SYSTEM FOR SIMULATION OF LOGIC AND MEMORY 审中-公开
标题翻译：用于模拟逻辑和存储器的硬件加速系统
公开(公告)号：WO2007064716A2
公开(公告)日：2007-06-07
申请号：PCT/US2006/045706
申请日：2006-11-29
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , WATT, William
发明人： VERHEYEN, Henry, T. , WATT, William
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F11/261 , G06F17/5022
摘要： A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation, hi one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, pre-determined offset to the user memory address. Thus, no address translation is required at run-time.
摘要翻译：硬件加速模拟器包括可由模拟处理器单独访问的存储存储器和程序存储器。程序存储器存储要执行的指令以便模拟芯片。存储存储器用于模拟用户存储器。由于程序存储器和存储存储器可以由模拟处理器单独访问，所以对用户存储器的读写的模拟不阻止程序存储器和仿真处理器之间的指令传送，从而提高了仿真的速度。一方面，通过向用户存储器地址添加固定的预定偏移量，将用户存储器地址映射到存储器存储器地址。因此，在运行时不需要地址转换。

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