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1. 发明申请

WO2005013324A3 MEMORY ACCESS VIA SERIAL MEMORY INTERFACE 审中-公开
标题翻译：通过串行存储器接口访问存储器
公开(公告)号：WO2005013324A3
公开(公告)日：2005-06-02
申请号：PCT/US2004023298
申请日：2004-07-16
申请人： LATTICE SEMICONDUCTOR CORP
发明人： ZHANG FULONG , SCHOLZ HAL , CHEN ZHENG
IPC分类号： G11C5/06 , H03K19/177
CPC分类号： H03K19/17756 , G11C5/066 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.
摘要翻译：本文公开了系统和方法以提供对可编程逻辑器件内的存储器单元的访问。例如，根据本发明的实施例，串行存储器接口与可编程逻辑器件内的每个特殊功能块相关联，以提供对特殊功能块的配置存储器单元的访问。

2. 发明申请

WO2004084000A3 PROGRAMMABLE LOGIC DEVICES WITH INTEGRATED STANDARD-CELL LOGIC BLOCKS 审中-公开
标题翻译：具有集成标准单元逻辑块的可编程逻辑器件
公开(公告)号：WO2004084000A3
公开(公告)日：2004-12-09
申请号：PCT/US2004001014
申请日：2004-01-16
申请人： LATTICE SEMICONDUCTOR CORP
发明人： ANDREWS WILLIAM , SCHADT JOHN , CHEN ZHENG , MYERS ANTHONY , RHEIN DAVID , ZIEGENFUS WARREN , ZHANG FULONG , DING MING , FENSTERMAKER LARRY
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17796
摘要： A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
摘要翻译：具有可编程逻辑核心，块存储器和I / O电路的可编程逻辑器件（PLD）具有集成到PLD设计中的一个或多个标准单元逻辑块（SLB），以使每个SLB可编程地连接到任何一个或多个可编程内核，块存储器和/或I / O电路。基于标准单元的功能块的添加创建了具有增加的总体逻辑密度的PLD，相对于等效的常规PLD（例如FPGA），每个功能的净尺寸，每个功能的净模具尺寸，降低的成本以及功率和性能特性的改善。

3. 发明申请

WO2007019339A3 CLOCK-AND-DATA-RECOVERY SYSTEM 审中-公开
标题翻译：时钟和数据恢复系统
公开(公告)号：WO2007019339A3
公开(公告)日：2008-01-03
申请号：PCT/US2006030501
申请日：2006-08-07
申请人： LATTICE SEMICONDUCTOR CORP
发明人： JOHNSON PHILLIP , CHEN ZHENG , BRITTON BARRY
IPC分类号： H04L7/02
CPC分类号： H04L7/0338 , H03L7/0812
摘要： A clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.
摘要翻译：时钟和数据恢复（CDR）系统具有产生相位偏移时钟信号和一个或多个信道电路的多相时钟发生器，每个信道电路接收（不同的）输入数据信号和所有相位偏移时钟信号并产生输出数据流和恢复的时钟信号。每个通道电路具有数据寄存器（例如，触发器），每个在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号，使得触发器被触发在输入数据信号的每个（上升）边沿。通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号信号。

4. 发明申请

WO2005041251A3 DIGITALLY CONTROLLED DELAY CELLS 审中-公开
标题翻译：数字控制延迟细胞
公开(公告)号：WO2005041251A3
公开(公告)日：2005-07-28
申请号：PCT/US2004016041
申请日：2004-05-13
申请人： LATTICE SEMICONDUCTOR CORP
发明人： ZHANG FULONG , ANDREWS WILLIAM , JOHNSON PHILLIP , SCHOLZ HAL , CHEN ZHENG , SCHADT JOHN
IPC分类号： G06F7/38 , H01L20060101 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0805
摘要： Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
摘要翻译：本文公开了用于实现集成电路中的信号延迟的系统和方法。例如，根据本发明的实施例，主延迟电路可以数字地控制一个或多个从延迟单元以支持可编程逻辑器件的各种应用。

5. 发明申请

WO2005048454A2 MULTIPLEXER CIRCUITS 审中-公开
标题翻译：多路复用器电路
公开(公告)号：WO2005048454A2
公开(公告)日：2005-05-26
申请号：PCT/US2004032665
申请日：2004-10-05
申请人： LATTICE SEMICONDUCTOR CORP
发明人： NGUYEN LIEM , HE XIAOJIE , ROGERS AARON , GAIDE BRIAN , ILGENTSTEIN KERRY , STANLEY CLAUDIA , WIJESURIYA SAJITHA , CHEN ZHENG
IPC分类号： H03K3/356 , H03K17/693 , H03K19/094
CPC分类号： H03K3/356008 , H03K17/693
摘要： Multiplexer circuits are disclosed, such as for example for programmable logic devices. As an example of one embodiment, a multiplexer circuit is disclosed having a default state and a state-locking latch.
摘要翻译：公开了多路复用器电路，例如用于可编程逻辑器件。作为一个实施例的例子，公开了一种具有默认状态和状态锁定锁存器的多路复用器电路。

6. 发明申请

WO2005002052A3 BI-DIRECTIONAL BUFFERING FOR MEMORY DATA LINES 审中-公开
标题翻译：存储器数据线的双向缓冲
公开(公告)号：WO2005002052A3
公开(公告)日：2005-03-31
申请号：PCT/US2004016103
申请日：2004-05-20
申请人： LATTICE SEMICONDUCTOR CORP
发明人： FENSTERMAKER LARRY , CARTNEY GREGORY , CHEN ZHENG
IPC分类号： G11C7/12 , G11C11/419 , G11C5/06
CPC分类号： G11C7/12 , G11C11/419
摘要： Systems and methods are disclosed for implementing configuration memory (200) on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers (2004) are implemented between sections (2002) of a column of memory. The buffers (204) may provide buffering for data lines (210) extending through the column of memory.
摘要翻译：公开了用于在可编程逻辑器件上实现配置存储器（200）的系统和方法。例如，根据本发明的一个实施例，双向缓冲器（2004）在存储器列的部分（2002）之间实现。缓冲器（204）可以为延伸通过存储器列的数据线（210）提供缓冲。

7. 发明申请

WO2007070766A2 JITTER TOLERANT DELAY-LOCKED LOOP CIRCUIT 审中-公开
标题翻译：抖动延迟延迟环路电路
公开(公告)号：WO2007070766A2
公开(公告)日：2007-06-21
申请号：PCT/US2006061763
申请日：2006-12-07
申请人： LATTICE SEMICONDUCTOR CORP
发明人： ZHANG FULONG , CHEN ZHENG , JOHNSON PHILLIP
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/12
摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.
摘要翻译：本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个控制信号。算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

8. 发明申请

WO2005020491A3 PROGRAMABLE BROADCAST INITIALIZATION OF MEMORY BLOCKS 审中-公开
标题翻译：存储块的可编程广播初始化
公开(公告)号：WO2005020491A3
公开(公告)日：2005-04-21
申请号：PCT/US2004022995
申请日：2004-07-16
申请人： LATTICE SEMICONDUCTOR CORP
发明人： CHEN ZHENG , SCHADT JOHN , BRITTON BARRY
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.
摘要翻译：本文公开了用于初始化可编程逻辑器件的存储块的系统和方法。例如，根据本发明的实施例，为用作单向广播写入总线的存储块提供系统总线扩展。读总线也可以被提供以读取存储在存储块中的数据。

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