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1. 发明申请

WO2007065090A3 PSEUDO-DYNAMIC WORD-LINE DRIVER 审中-公开
公开(公告)号：WO2007065090A3
公开(公告)日：2008-05-15
申请号：PCT/US2006061299
申请日：2006-11-28
申请人： LATTICE SEMICONDUCTOR CORP
发明人： FENSTERMAKER LARRY , CARTNEY GREGORY
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.
摘要翻译：在某些实施例中，本发明是用于地址解码器的字线驱动器，其解码多位地址以使得能够访问电路元件行，例如在专用存储器件中实现的存储器块中的存储器单元，或者如更大的器件的一部分，如FPGA。字线驱动器具有用于每个字线的反馈锁存器，以确保当该字线未被选择用于访问时字线不通电。通过使用解码的地址位值而不是一些现有技术的动态字线驱动器的预充电使能信号控制反馈锁存器，字线驱动器防止多个字线的不期望的通电。可以使用比一些类似的现有技术的静态字线驱动器更少的布局面积和更少的功率来实现字线驱动器。

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