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1. 发明申请

WO2005020491A3 PROGRAMABLE BROADCAST INITIALIZATION OF MEMORY BLOCKS 审中-公开
标题翻译：存储块的可编程广播初始化
公开(公告)号：WO2005020491A3
公开(公告)日：2005-04-21
申请号：PCT/US2004022995
申请日：2004-07-16
申请人： LATTICE SEMICONDUCTOR CORP
发明人： CHEN ZHENG , SCHADT JOHN , BRITTON BARRY
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.
摘要翻译：本文公开了用于初始化可编程逻辑器件的存储块的系统和方法。例如，根据本发明的实施例，为用作单向广播写入总线的存储块提供系统总线扩展。读总线也可以被提供以读取存储在存储块中的数据。

2. 发明申请

WO2004073175A3 ADAPTIVE INPUT LOGIC FOR PHASE ADJUSTMENTS 审中-公开
标题翻译：用于相位调整的自适应输入逻辑
公开(公告)号：WO2004073175A3
公开(公告)日：2005-01-20
申请号：PCT/US2004001556
申请日：2004-01-16
申请人： LATTICE SEMICONDUCTOR CORP
发明人： ANDREWS WILLIAM , SCHOLZ HAROLD , BRITTON BARRY
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081 , H04B20060101 , H04L7/033
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0818 , H04L7/0041 , H04L7/0337
摘要： Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.
摘要翻译：公开了系统和方法以相对于时钟信号为数据信号提供静态和/或动态相位调整。例如，数据信号可以被延迟粗略的延迟和/或精细的延迟，以针对每个输入路径（例如，每个输入焊盘）独立地匹配时钟信号的定时。延迟可以是正和/或负时钟边缘的函数。

3. 发明申请

WO2007019339A3 CLOCK-AND-DATA-RECOVERY SYSTEM 审中-公开
标题翻译：时钟和数据恢复系统
公开(公告)号：WO2007019339A3
公开(公告)日：2008-01-03
申请号：PCT/US2006030501
申请日：2006-08-07
申请人： LATTICE SEMICONDUCTOR CORP
发明人： JOHNSON PHILLIP , CHEN ZHENG , BRITTON BARRY
IPC分类号： H04L7/02
CPC分类号： H04L7/0338 , H03L7/0812
摘要： A clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.
摘要翻译：时钟和数据恢复（CDR）系统具有产生相位偏移时钟信号和一个或多个信道电路的多相时钟发生器，每个信道电路接收（不同的）输入数据信号和所有相位偏移时钟信号并产生输出数据流和恢复的时钟信号。每个通道电路具有数据寄存器（例如，触发器），每个在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号，使得触发器被触发在输入数据信号的每个（上升）边沿。通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号信号。

4. 发明申请

WO2006091527A3 DISTRIBUTED MULTIPLE-CHANNEL ALIGNMENT SCHEME 审中-公开
标题翻译：分布式多通道对准方案
公开(公告)号：WO2006091527A3
公开(公告)日：2007-05-31
申请号：PCT/US2006005940
申请日：2006-02-21
申请人： LATTICE SEMICONDUCTOR CORP
发明人： LEUNG WAI-BOR , BRITTON BARRY , SUBRAMANIAM AKILA
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： H04L25/14
摘要： A channel-alignment circuit (100) has a controller (102) and a plurality of channel-alignment blocks (104(0)404(7)). Each channel- alignment block (104(0)-104(7)) synchronizes two or more channels. The controller (102) coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.
摘要翻译：通道对准电路（100）具有控制器（102）和多个通道对准块（104（0）404（7））。每个通道对齐块（104（0）-104（7））同步两个或更多个通道。控制器（102）通过块协调通道的同步，使得（i）两个或更多个块的一个或多个组中的每一个中的信道被同步，并且（ii）每组块独立于任何其他组被同步。

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