专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004077498A2 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2004077498A2
公开(公告)日：2004-09-10
申请号：PCT/IB2004/050113
申请日：2004-02-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , PONOMAREV, Youri , HOOKER, Jacob, C.
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , PONOMAREV, Youri , HOOKER, Jacob, C.
IPC分类号： H01L
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/66825
摘要： In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9). A second sacrificial layer (20) is used to protect the part (82) off the surface (2) adjacent to the second sidewall (81) and opposite to the position (83) of the second stack (7) when providing the access gate layer (14).
摘要翻译：在制造半导体器件（100）的方法中，其包括具有源极区（3）的表面（2）和限定沟道方向（102）的漏极区（4）的半导体（1）和通道区域（101），在沟道区域（101）的顶部上的第一层叠层（6），第一堆叠（6）依次包括隧道介电层（11），电荷存储层（10）用于在通道方向（102）上直接与第一堆叠（6）相邻的通道区域（101）的顶部上存储电荷和控制栅极层（9）以及第二堆叠（7），第二堆叠（7）包括与半导电体（1）和第一堆叠（6）电绝缘的存取栅极层（14），最初使用第一牺牲层（90），其随后由控制栅极层（9）。当提供接入门（20）时，第二牺牲层（20）用于保护邻近第二侧壁（81）的表面（2）并且与第二堆叠（7）的位置（83）相对的部分（82）层（14）。

2. 发明申请

WO2005022648A1 METHOD OF FABRICATING A DOUBLE GATE FIELD EFFECT TRANSISTOR DEVICE, AND SUCH A DOUBLE GATE FIELD EFFECT TRANSISTOR DEVICE 审中-公开
标题翻译：制造双门控场效应晶体管器件的方法，以及双门控场效应晶体管器件
公开(公告)号：WO2005022648A1
公开(公告)日：2005-03-10
申请号：PCT/IB2004/051454
申请日：2004-08-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu Catalin , PONOMAREV, Youri
发明人： SURDEANU, Radu Catalin , PONOMAREV, Youri
IPC分类号： H01L29/786
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/4908 , H01L29/78621 , H01L29/78648
摘要： The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.
摘要翻译：本发明公开了一种形成双栅场效应晶体管器件的方法，以及用该方法形成的器件。一个从绝缘体上半导体衬底开始，并形成第一个栅极，源极，漏极和延伸部分，并准备第二个栅极。然后将衬底接合到第二载体，暴露半导体层的第二侧。接下来，进行退火步骤作为无扩散退火，其优点是半导体层不仅具有基本上均匀的厚度，而且具有基本平坦的表面。这确保了所述退火步骤的最佳退火作用。通过非常高的掺杂剂活化，实现了延伸部的非常尖锐的突然性。

3. 发明申请

WO2008038197A1 BRANCHING THERAPY ELEMENTS AND METHOD OF THEIR INSERTION INTO LIVING TISSUE 审中-公开
标题翻译：分配治疗单元及其入侵组织的方法
公开(公告)号：WO2008038197A1
公开(公告)日：2008-04-03
申请号：PCT/IB2007/053824
申请日：2007-09-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , PONOMAREV, Youri , MERZ, Matthias , PIJNENBURG, Remco Henricus Wilhelmus
发明人： PONOMAREV, Youri , MERZ, Matthias , PIJNENBURG, Remco Henricus Wilhelmus
IPC分类号： A61N1/05
CPC分类号： A61N1/0529 , A61N1/0534
摘要： An implantable medical system for electrical recording and or providing therapy to a plurality of tissue sites without damage to surrounding blood vessels is disclosed comprising: an implant body having a plurality of therapy elements, the elements being hingedly attached at one end to the surface of the body and releasably extendable outward from the surface of the body at the other end; a release mechanism for each of the elements; and a coating material covering the body and the elements; wherein upon dissolution of the coating material after implantation, the release mechanism is capable of causing the elements to extend outward at one end from the surface of the body and into a plurality of tissue sites without damage to the surrounding blood vessels. The method of implanting the system into a body is also disclosed.
摘要翻译：公开了一种用于对多个组织部位进行电记录和/或对周围血管的损伤提供治疗的可植入医疗系统，包括：具有多个治疗元件的植入体，所述元件在一端铰接附接到并且在另一端从主体的表面可释放地向外延伸; 用于每个元件的释放机构; 以及覆盖所述主体和所述元件的涂层材料; 其中，在植入后溶解涂层材料时，释放机构能够使元件在一端从身体的表面向外延伸并且进入多个组织部位而不损坏周围的血管。还公开了将系统植入体内的方法。

4. 发明申请

WO2007010441A3 APPARATUS AND METHOD FOR COUPLING IMPLANTED ELECTRODES TO NERVOUS TISSUE 审中-公开
公开(公告)号：WO2007010441A3
公开(公告)日：2007-01-25
申请号：PCT/IB2006/052348
申请日：2006-07-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , U.S. PHILIPS CORPORATION , MERZ, Matthias , PONOMAREV, Youri , PIJNENBURG, Remco
发明人： MERZ, Matthias , PONOMAREV, Youri , PIJNENBURG, Remco
IPC分类号： A61N1/05 , A61N1/36 , A61B5/04
摘要： An apparatus and method for improving electrical contact between an implanted device (10) for recording or stimulating neuronal activity and surrounding tissue (12) (e.g., brain tissue, nerve fibers, etc.). In an exemplary embodiment, a nanometer sized topographic structure (36, 136) (e.g., a nanometer scale pillar) is processed for electrical connection with a corresponding electrode (30, 32) of the implanted device (10). The nanometer scale topographic structure (36, 136) bridges a gap (26) between the implanted device (10) and surrounding tissue (12), thus improving neuron-electrode coupling therebetween. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells (20) can be used for sensing and/or stimulation thereof.

5. 发明申请

WO2005117132A1 PLANAR DUAL GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：平面双栅半导体器件
公开(公告)号：WO2005117132A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051681
申请日：2005-05-24
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LOO, Josine , PONOMAREV, Youri
发明人： LOO, Josine , PONOMAREV, Youri
IPC分类号： H01L29/786
CPC分类号： H01L29/42384 , H01L29/665 , H01L29/66553 , H01L29/66613 , H01L29/66621 , H01L29/66772 , H01L29/78648
摘要： A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.
摘要翻译：提供一种制造双栅极半导体器件的方法，其中在第一栅极（12）形成在第一栅极（12）的第一表面（14）的一部分上之后，进行源极和漏极接触区域（34,36）的硅化，硅体（16）之前，但是在与第一表面相对的硅体的第二表面（44）上形成第二栅极（52）之前。第一栅极（12）用作掩模以确保硅化源极和漏极接触区域与硅沟道（18）对准。此外，通过在制造的早期进行硅化，第二栅极的材料的选择不受任何高温工艺的限制。有利的是，由硅化产生的硅体第二表面的材料特性的差异使得第二栅极能够在硅化物源极和漏极接触区域之间横向排列。

6. 发明申请

WO2005076331A1 METHOD OF FABRICATING METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES. 审中-公开
标题翻译：制备金属氧化物半导体集成电路器件的方法。
公开(公告)号：WO2005076331A1
公开(公告)日：2005-08-18
申请号：PCT/IB2005/000248
申请日：2005-01-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , STOLK, Peter , PONOMAREV, Youri
发明人： STOLK, Peter , PONOMAREV, Youri
IPC分类号： H01L21/28
CPC分类号： H01L29/517 , H01L21/26506 , H01L21/28167 , H01L21/28176 , H01L21/28194 , H01L21/324 , H01L21/823807 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/518
摘要： The present invention relates to a method of fabricating metal-oxide semiconductor integrated circuit devices. Said fabrication method comprises the steps of: - forming a dielectric layer (111) on a substrate, - forming a gate electrode (112) on said dielectric layer, - implanting passivating impurities (121) in the substrate, and - performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment. The gate electrode is, for example, a metallic gate electrode. The step of implanting passivating impurities in the substrate is performed, for example, through the metallic gate electrode and the dielectric layer. The passivating impurities are chosen, for example, among hydrogen, deuterium, fluorine, nitrogen or chlorine.
摘要翻译：本发明涉及金属氧化物半导体集成电路器件的制造方法。所述制造方法包括以下步骤： - 在衬底上形成电介质层（111）， - 在所述电介质层上形成栅电极（112）， - 在所述衬底中注入钝化杂质（121），以及 - 执行热处理所述钝化杂质适于在所述热处理期间钝化介电层内的介电缺陷。栅电极例如是金属栅电极。在衬底中注入钝化杂质的步骤例如通过金属栅电极和电介质层进行。选择钝化杂质，例如氢，氘，氟，氮或氯。

7. 发明申请

WO2007080460A1 APPARATUS AND METHOD FOR ELECTROSTIMULATION/SENSING IN VIVO 审中-公开
标题翻译： VIVO中电感/感觉的装置和方法
公开(公告)号：WO2007080460A1
公开(公告)日：2007-07-19
申请号：PCT/IB2006/053259
申请日：2006-09-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , PONOMAREV, Youri , MERZ, Matthias , PIJNENBURG, Remco
发明人： PONOMAREV, Youri , MERZ, Matthias , PIJNENBURG, Remco
IPC分类号： A61N1/05
CPC分类号： A61N1/0551 , A61N1/40
摘要： An apparatus and method for electrostimulation treatment of neurological diseases is disclosed herein. The apparatus and method include an array (22) of sub-micron (and sub-cell size) FET electrodes (24) that are capacitively coupled to nervous system elements (both neurons (50) and axons(66)) as a replacement for traditional metal shanks in both single-and multi- electrode(s) electrostimulation implantable devices. By using such an approach, significant improvements in selectivity, power consumption and biocompatibility can be achieved, as well as relying on mainstream IC manufacture techniques for the manufacture thereof, making it cost- effective. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells can be used for sensing and/or stimulation thereof.
摘要翻译：本文公开了神经疾病的电刺激治疗的装置和方法。该装置和方法包括电容耦合到神经系统元件（神经元（50）和轴突（66））的亚微米（和子电池尺寸）FET电极（24）的阵列（22）传统的金属柄在单电极和多电极的电刺激可植入装置中。通过使用这种方法，可以实现选择性，功率消耗和生物相容性的显着改善，以及依靠主流IC制造技术来制造它，从而使其具有成本效益。本公开还可以扩展到任何可以将单个或多个单元的电容耦合用于感测和/或刺激的应用。

8. 发明申请

WO2005004241A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A QUANTUM WELL STRUCTURE AND A SEMICONDUCTOR DEVICE COMPRISING SUCH A QUANTUM WELL STRUCTURE 审中-公开
标题翻译：半导体器件，制造量子阱结构的方法和包含这种量子阱结构的半导体器件
公开(公告)号：WO2005004241A1
公开(公告)日：2005-01-13
申请号：PCT/IB2004/051040
申请日：2004-06-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PONOMAREV, Youri
发明人： PONOMAREV, Youri
IPC分类号： H01L29/778
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/152 , H01L29/7782 , H01L29/7838 , H01L29/78687 , Y10S438/962
摘要： A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6'), wherein the material of the insulating layers (6,6') has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 mn gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
摘要翻译：公开了一种用于在基板（2）上获得具有量子阱结构（4）的多层结构（3）的半导体器件（1）和方法。量子阱结构（4）包括被绝缘层（6,6'）夹持的半导体层（5），其中绝缘层（6,6'）的材料优选具有高的介电常数。在FET中，量子阱（4,9）用作通道，允许更高的驱动电流和更低的截止电流。短信道效应降低。多通道FET适用于三分之三十五m栅极长度的工作。在该方法中，通过高介电常数材料和半导体材料彼此交替地外延生长，优选地以MBE形成量子阱。

9. 发明申请

WO2003065437A2 METHOD AND DEVICE TO FORM HIGH QUALITY OXIDE LAYERS OF DIFFERENT THICKNESS IN ONE PROCESSING STEP 审中-公开
标题翻译：在一个加工步骤中形成不同厚度的高质量氧化物层的方法和装置
公开(公告)号：WO2003065437A2
公开(公告)日：2003-08-07
申请号：PCT/IB2003/000136
申请日：2003-01-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LOO, Josine, J., G., P. , PONOMAREV, Youri , SCHAIJK, Robertus, T., F.
发明人： LOO, Josine, J., G., P. , PONOMAREV, Youri , SCHAIJK, Robertus, T., F.
IPC分类号： H01L21/316
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/31662 , H01L21/823462 , H01L21/823468 , H01L27/115 , H01L27/11524 , H01L29/66825
摘要： The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: a) doping the first and the second semiconductor region with a different dopant concentration, and b) oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500°C and 700°C, preferably between 500°C and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rateincrease.
摘要翻译：本发明涉及在一个处理步骤中在第一和第二半导体区域上形成不同厚度的高质量氧化物层的方法。该方法包括以下步骤：a）以不同的掺杂剂浓度掺杂第一和第二半导体区域，以及b）在相同的处理步骤期间，在500℃与第二半导体区域之间的温度下氧化第一和第二半导体区域 700℃，优选在500℃至650℃之间。还提供相应的装置。使用低掺杂浓度的低温氧化会导致意想不到的氧化速率增加。

10. 发明申请

WO2006038164A1 SEMICONDUCTOR DEVICE HAVING SUBSTRATE COMPRISING LAYER WITH DIFFERENT THICKNESSES AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有包含不同厚度的层的基板的半导体器件及其制造方法
公开(公告)号：WO2006038164A1
公开(公告)日：2006-04-13
申请号：PCT/IB2005/053215
申请日：2005-09-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PONOMAREV, Youri
发明人： PONOMAREV, Youri
IPC分类号： H01L29/786 , H01L21/336 , H01L29/06 , H01L27/12 , H01L21/84
CPC分类号： H01L29/0684 , H01L21/26533 , H01L21/266 , H01L21/84 , H01L27/1203 , H01L27/1255 , H01L29/66772 , H01L29/78603 , H01L29/78645 , H01L29/78657 , H01L29/78696
摘要： This invention relates to a semiconductor device and a method of manufacturing this device. An embodiment of the semiconductor device (100) according to the invention comprises a semiconductor body (102) with a surface (107), the semiconductor body (102) further comprising an active part (130) positioned at the surface (107), a substrate part (210) and an insulating layer (220) located between the active part (130) and the substrate part (210). The active part (130) comprises three parts (A1,A2,A3), each part having a thickness (Tl,T2,T3), the thickness (TI,T2,T3) being measured at right angles to the surface (107), and the thickness within each area (A1,A2,A3) being substantially uniform. In each area (A1,A2,A3) a transistor (Nl,N2,N3) is present. Each transistor (N1,N2,N3) comprises a source (Sl,S2,S3), a drain (Dl,D2,D3) and a channel region which extends between the source (Sl,S2,S3) and the drain (Dl,D2,D3), wherein the source (S1,S2,S3), the drain (D,D2,D3) and the channel region (CH1,CH2,CH3) are located under the surface (107) of the semiconductor body (102). Each transistor (N1,N2,N3) further comprises a gate (G1,G2,G3) located above the surface (107) of the semiconductor body (102).
摘要翻译：本发明涉及一种半导体器件及其制造方法。根据本发明的半导体器件（100）的实施例包括具有表面（107）的半导体本体（102），所述半导体本体（102）还包括位于所述表面（107）处的有源部分（130），衬底部分（210）和位于有源部分（130）和衬底部分（210）之间的绝缘层（220）。活动部分（130）包括三个部分（A1，A2，A3），每个部分具有厚度（T1，T2，T3），与表面（107）成直角测量的厚度（TI，T2，T3），并且每个区域（A1，A2，A3）内的厚度基本上均匀。在每个区域（A1，A2，A3）中存在晶体管（N1，N2，N3）。每个晶体管（N1，N2，N3）包括源（S1，S2，S3），漏极（D1，D2，D3）和在源极（S1，S2，S3）和漏极（D1）之间延伸的沟道区，D2，D3），其中源（S1，S2，S3），漏极（D，D2，D3）和沟道区（CH1，CH2，CH3）位于半导体主体的表面（107） 102）。每个晶体管（N1，N2，N3）还包括位于半导体本体（102）的表面（107）上方的栅极（G1，G2，G3）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式