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1. 发明申请

WO2005076478A1 LATCH CIRCUIT 审中-公开
标题翻译：锁定电路
公开(公告)号：WO2005076478A1
公开(公告)日：2005-08-18
申请号：PCT/IB2005/050286
申请日：2005-01-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , CISSÉ, Idrissa
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , CISSÉ, Idrissa
IPC分类号： H03K19/086
CPC分类号： H03K3/356043
摘要： A latch circuit (1) comprising, a differential input with an inverting input (D+) and a non-inverting input (D-). The latch further comprises a differential output with an inverting output (Q+) and a non-inverting output (Q-). One of the outputs (Q-) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (V cM ) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output s in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold, respectively.
摘要翻译：一种锁存电路（1），包括具有反相输入（D +）和非反相输入（D-）的差分输入。锁存器还包括具有反相输出（Q +）和非反相输出（Q-）的差分输出。输出（Q-）中的一个耦合到具有相反极性的输入（D +）之一。锁存器还包括控制输入，用于接收用于确定输入信号（In）的阈值的控制信号（VcM），使得如果输入信号大于阈值，则非反相输出s处于HIGH逻辑状态，以及如果输入信号分别小于阈值，则处于LOW状态。

2. 发明申请

WO2007057804A1 POLAR MODULATION APPARATUS AND METHOD WITH COMMON-MODE CONTROL 审中-公开
标题翻译：极性调制装置和方法与共模控制
公开(公告)号：WO2007057804A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/054040
申请日：2006-11-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , ADITHAM, Ram, P. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , ADITHAM, Ram, P. , STIKVOORT, Eduard, F.
IPC分类号： H03C5/00
CPC分类号： H03C5/00
摘要： The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry(30) and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry(30). A bias input of the differential power amplifier circuitry(30) is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry(30). Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.
摘要翻译：本发明涉及极化调制装置和方法，其中基于输入信号的分别处理的相位调制（PM）和调幅（AM）分量产生极调调制信号。通过使用差分功率放大器电路（30）根据相位调制和幅度调制分量产生放大的极化调制输出信号，并将放大的相位调制分量提供给差分功率放大器电路（30）的差分输入。基于幅度调制分量来控制差分功率放大器电路（30）的偏置输入，以便调制差分功率放大器电路（30）的共模电流。因此，可以实现具有静态DC-DC转换器和功率和/或效率和/或线性控制的输出功率放大器的极性调制器的新概念。

3. 发明申请

WO2006109214A1 BROADBAND AMPLIFIER 审中-公开
标题翻译：宽带放大器
公开(公告)号：WO2006109214A1
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051033
申请日：2006-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： H03F3/195 , H03F3/347 , H03F3/343 , H03F1/34 , H03G3/30
CPC分类号： H03F3/3432 , H03F1/34 , H03F3/195 , H03F3/347 , H03F2200/09 , H03F2200/144 , H03F2200/294 , H03F2200/36 , H03F2200/372
摘要： A broadband amplifier (2) for receiving radio frequency signals from an antenna (4) is disclosed. The amplifier comprises a first amplifier stage (6) for receiving an input voltage signal, and a first feedback stage (12) for providing a feedback link between an input and an output of the first amplifier stage (6). A second amplifier stage (10) is connected to an output of the first amplifier stage (6) and a second feedback stage (16) provides a feedback link from an output of the second amplifier stage to an input of the first amplifier stage. An output voltage signal is provided at an output terminal (22) of an output stage (20).
摘要翻译：公开了一种用于从天线（4）接收射频信号的宽带放大器（2）。放大器包括用于接收输入电压信号的第一放大级（6）和用于在第一放大级（6）的输入和输出之间提供反馈链路的第一反馈级（12）。第二放大器级（10）连接到第一放大器级（6）的输出，第二反馈级（16）提供从第二放大器级的输出到第一放大级的输入的反馈链路。在输出级（20）的输出端（22）处提供输出电压信号。

4. 发明申请

WO2005041413A1 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：WO2005041413A1
公开(公告)日：2005-05-06
申请号：PCT/IB2004/052080
申请日：2004-10-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , STIKVOORT, Eduard, F. , SANDULEANU, Mihai, A., T.
发明人： STIKVOORT, Eduard, F. , SANDULEANU, Mihai, A., T.
IPC分类号： H03K23/54
CPC分类号： H03K23/44 , H03K23/542
摘要： A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency divider further comprises a second flip-flop (M'1, M'2, M'3, M'4) having a second clock input (Cl) for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input (Cl), a second set input coupled to the first non-inverted output (Q1), a second non-inverted output (Q2) and a second inverted output (Q2), the second inverted output (Q2) being coupled to the first set input (Q4).
摘要翻译：一种分频器，包括具有用于接收时钟信号的第一时钟输入（CI）的第一触发器（M1，M2，M3，M4），所述触发器还包括第一设定输入（Q4）和第一非 - 反相输出（Q1）。分频器还包括具有第二时钟输入（C1）的第二触发器（M'1，M'2，M'3，M'4），用于接收与第二时钟信号基本上相反的第二时钟信号输入到第一时钟输入（C1）的时钟信号，耦合到第一非反相输出（Q1）的第二设定输入，第二非反相输出（Q2）和第二反相输出（Q2），第二反相输出（Q2）耦合到第一组输入（Q4）。

5. 发明申请

WO2005041412A1 PRESCALER 审中-公开
标题翻译：预分频器
公开(公告)号：WO2005041412A1
公开(公告)日：2005-05-06
申请号：PCT/IB2004/052079
申请日：2004-10-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： H03K23/54
CPC分类号： H03K23/44 , H03K23/542
摘要： A prescaler, comprising a first flip-flop (F1) coupled to a second flip-flip (F2). Each flip-flop comprises a latch (M1, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) and second NOR circuit (M5, M6, M7).
摘要翻译：一种预分频器，包括耦合到第二触发器（F2）的第一触发器（F1）。每个触发器包括具有耦合到相应的第一NOR电路（M8，M9，M10）和第二NOR电路（M5）的第一输入（R）和第二输入（S）的锁存器（M1，M2，M3，M4） M6，M7）。

6. 发明申请

WO2007036849A1 VARACTOR-LESS OSCILLATOR WITH ENHANCED TUNING CAPABILITY 审中-公开
标题翻译：具有增强调谐能力的无极振荡器
公开(公告)号：WO2007036849A1
公开(公告)日：2007-04-05
申请号：PCT/IB2006/053403
申请日：2006-09-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , IONITA, Razvan-Adrian
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , IONITA, Razvan-Adrian
IPC分类号： H03B5/12 , H03K3/354
CPC分类号： H03B27/00 , H03B5/1212 , H03B5/1218 , H03B5/1228 , H03B5/1265 , H03B5/1271 , H03B2200/0074
摘要： The present invention relates to a differential oscillator circuit and a method of controlling the frequency of an oscillator signal. An enhanced frequency tuning mechanism is provided for controlling the frequency of the oscillator signal. The frequency tuning mechanism comprises first frequency control circuitry for controlling the threshold voltage of respective load transistors (M3, M4) of the differential oscillator circuit, and second frequency control circuitry for controlling at least one of a common-mode current (I BIAS ) flowing through branches of said differential oscillator circuit, a tail current (I TUNE ) of an additional feedback circuit (M5, M6) cross-coupled between the drains of a differential transistor stage (Ml, M2) of said differential oscillator and respective gates of said load transistors (M3, M4), and a voltage applied at a middle point of a tapped coil of a resonating circuit of the differential oscillator circuit. Thereby, a linear fine tuning characteristic can be obtained, where the tuning mechanism may for example work as a "gear-box" by stepping coarsely with the first frequency control circuitry through fine intervals generated by the second frequency control circuitry.
摘要翻译：本发明涉及一种差分振荡器电路和一种控制振荡器信号的频率的方法。提供了一种用于控制振荡器信号的频率的增强型频率调谐机构。频率调谐机构包括用于控制差分振荡器电路的各个负载晶体管（M3，M4）的阈值电压的第一频率控制电路，以及用于控制共模电流（I SUB）中的至少一个的第二频率控制电路， BIAS）流过所述差分振荡器电路的分支，在差动晶体管级的漏极之间交叉耦合的附加反馈电路（M5，M6）的尾电流（IOUT TUNE＆lt; / SUB）（M1，M2）和所述负载晶体管（M3，M4）的各个栅极以及施加在差分振荡器电路的谐振电路的抽头线圈的中点处的电压。由此，可以获得线性微调特性，其中调谐机构可以例如通过与第一频率控制电路粗略地步进通过由第二频率控制电路产生的精细间隔而作为“变速箱”工作。

7. 发明申请

WO2007012993A3 TRANSISTOR BULK CONTROL FOR COMPENSATING FREQUENCY AND/OR PROCESS VARIATIONS 审中-公开
公开(公告)号：WO2007012993A3
公开(公告)日：2007-02-01
申请号：PCT/IB2006/052389
申请日：2006-07-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IONITA, Razvan-Adrian , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： IONITA, Razvan-Adrian , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： H03K17/14
摘要： The present invention relates to a method and apparatus for controlling a bulk voltage supplied to at least one transistor means of a controlled circuit (260) of an integrated circuit, wherein at least one sensing transistor means is provided adjacent to the at least one transistor means of the controlled circuit (260), and at least one reference transistor means is provided at a location remote from the at least one transistor means of the controlled circuit (260). A predetermined bias voltage is applied to the at least one reference transistor means, and the bulk voltage is controlled based on a comparison of a sensed threshold voltage of the at least one sensing transistor means and a sensed threshold voltage of the at least one reference transistor means. Thereby, process variation can be compensated. Alternatively or additionally, an information indicating a relation between a frequency information and a desired threshold voltage of the at least one transistor means of the controlled circuit (270) may be stored, and the bulk voltage may be controlled to an optimized value based on the stored relation with respect to a frequency of an input signal of the integrated circuit.

8. 发明申请

WO2006109216A1 MIXER CIRCUIT 审中-公开
标题翻译：混频器电路
公开(公告)号：WO2006109216A1
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051035
申请日：2006-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： H03D7/14
CPC分类号： H03D7/1433 , H03D7/1408 , H03D7/1425 , H03D7/1458 , H03D7/1475
摘要： A subharmonic mixer circuit having an input stage (52) and a current modulating stage (64) is disclosed. The input stage (52) receives an RF input signal (RF+, RF-) at a first frequency and generates output currents (il, i2) varying in dependence upon the Rf input signal. The current modulating stage (64) comprises a first transistor (Q3) for receiving a first local oscillator signal (LOO) respective and a second transistor (Q4) for receiving a second local oscillator signal (LOl 80), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (i0), having twice the local oscillator frequency, is superimposed onto the output currents.
摘要翻译：公开了具有输入级（52）和电流调制级（64）的次谐波混频电路。输入级（52）以第一频率接收RF输入信号（RF +，RF-），并产生根据Rf输入信号变化的输出电流（i1，i2）。电流调制级（64）包括用于接收相应的第一本地振荡器信号（LOO）的第一晶体管（Q3）和用于接收第二本地振荡器信号（LO180）的第二晶体管（Q4），与第第一本地振荡器信号，使得具有两倍本地振荡器频率的调制电流信号（i0）被叠加到输出电流上。

9. 发明申请

WO2005022819A1 PHASE DETECTOR 审中-公开
标题翻译：相位检测器
公开(公告)号：WO2005022819A1
公开(公告)日：2005-03-10
申请号：PCT/IB2004/051448
申请日：2004-08-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： H04L7/033
CPC分类号： H03D13/003 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/107 , H04L7/033
摘要： The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A transition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector comprises a first signal generator (42) for generating a first binary signal ERRQ, a pulse width of which is equal to a first time difference ΔT1 between a transition of the data signal DATA and a transition of a first reference clock signal CKQ adjacent to the transition of the data signal DATA, wherein the first signal generator comprises an input for receiving the first reference clock signal CKQ and an input for receiving the data signal DATA. The phase detector comprises a second signal generator (40) for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ΔT2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA, wherein the second signal generator (40) comprises an input for receiving the second binary signal ERRI and an input for receiving the second reference signal CKI. The phase detector comprises an output signal generator (40) for generating an output signal representative of the phase difference between the data clock DATA-CLK and the reference clock REF-CLK, wherein the output signal is equal to ERRQ - 2*(ERRQ AND ERRI) and AND represents a logical AND-operation or the output is equal to (ERRQ XOR ERRI) - ERRI, wherein XOR represents a logical XOR-operation.
摘要翻译：本发明涉及一种用于使用数据信号DATA检测数据时钟DATA-CLK和参考时钟REF-CLK之间的相位差的相位检测器。数据信号DATA的转换与数据时钟DATA-CLK的转换同步。数据时钟DATA-CLK和参考时钟REF-CLK具有相同的频率。相位检测器包括用于产生第一二进制信号ERRQ的第一信号发生器（42），其中脉冲宽度等于数据信号DATA的转变和第一参考时钟信号CKQ的转变之间的第一时间差ΔT1 与数据信号DATA的转换相邻，其中第一信号发生器包括用于接收第一参考时钟信号CKQ的输入端和用于接收数据信号DATA的输入端。相位检测器包括用于产生第二二进制信号ERRI的第二信号发生器（40）。第二二进制信号ERRI的脉冲宽度等于数据信号DATA的转变与与数据信号DATA的转变相邻的第二参考时钟信号CKI的转变之间的第二时间差ΔT2，其中第二信号发生器（40）包括用于接收第二二进制信号ERRI的输入端和用于接收第二参考信号CKI的输入端。相位检测器包括用于产生表示数据时钟DATA-CLK与参考时钟REF-CLK之间的相位差的输出信号的输出信号发生器（40），其中输出信号等于ERRQ-2 *（ERRQ AND ERRI），AND表示逻辑AND运算或输出等于（ERRQ XOR ERRI）-ERRI，其中XOR表示逻辑异或运算。

10. 发明申请

WO2004086409A1 CIRCUIT FOR USE IN FREQUENCY OR PHASE DETECTOR 审中-公开
标题翻译：用于频率或相位检测器的电路
公开(公告)号：WO2004086409A1
公开(公告)日：2004-10-07
申请号：PCT/IB2004/050310
申请日：2004-03-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC分类号： G11C27/02
CPC分类号： G11C27/024 , G01R25/005 , H03L7/085 , H03L7/087 , H04L7/033
摘要： A tracking data cell (10) comprising: - a pair of track and hold circuits (1, l') coupled to a first multiplexer (5), - a clock signal (H+, H-) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1') for determining a receipt of a data signal (D+, D-) having a rate, - said track and hold circuits (1, l') providing an output signal (O) having a substantially half rate.
摘要翻译：跟踪数据单元（10）包括： - 耦合到第一多路复用器（5）的一对跟踪和保持电路（1,1'）， - 时钟信号（H +，H-）基本上被反相输入用于确定具有速率的数据信号（D +，D-）的接收的相应的跟踪和保持电路（1,1'）， - 提供输出信号（O）的所述轨道和保持电路（1,1）大概是一半的。

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