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1. 发明申请

WO2005006580A1 RECEIVER FOR RECEIVING FREQUENCY SIGNALS USING DELTA-SIGMA MODULATORS 审中-公开
标题翻译：接收器使用DELTA-SIGMA调制器接收频率信号
公开(公告)号：WO2005006580A1
公开(公告)日：2005-01-20
申请号：PCT/IB2004/051096
申请日：2004-07-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WETZKER, Gunnar , LEENAERTS, Dominicus, M., W.
发明人： WETZKER, Gunnar , LEENAERTS, Dominicus, M., W.
IPC分类号： H04B1/26
CPC分类号： H04B1/0007 , H04B1/0003 , H04B1/28
摘要： Receivers (1,11) for receiving radio frequency signals are provided with modulating stages (4,14) between mixing stages (3,13) and filtering stages (5,15) for deltasigma modulating intermediate frequency signals, to shape the quantisation noise out of the frequency band in which the wanted channel is located. Modulating stages (4,14) comprise delta-sigma modulators (41,42,43,90) with low-pass filters (91), quantisers (92) and digitalto-analog converters (93) having a low resolution and therefore a low power consumption. Due to delta-sigma modulating being done through a feedback loop, the receivers (1,11) have become less critical. The low-pass filters (91) comprise time-continuous filters, to avoid antialiasing filtering. The receivers further comprise digital further mixing stages (6, 16) coupled to the filtering stages (5, 15) for generating baseband signals and digital further filtering stages (7, 17) coupled to the further mixing stages (6, 16) for channel selective filtering the baseband signals.
摘要翻译：用于接收射频信号的接收器（1,11）在混合级（3,13）和滤波级（5,15）之间设有调制级（4,14），用于解调中频信号，以量化噪声输出的所需频道所在的频带。调制级（4,14）包括具有低分辨率和低分辨率的低通滤波器（91），量化器（92）和数模转换器（93）的Δ-Σ调制器（41,42,43,90）能量消耗。由于通过反馈环路进行Δ-Σ调制，接收器（1,11）已经变得不太关键。低通滤波器（91）包括时间连续滤波器，以避免抗混叠滤波。接收器还包括耦合到滤波级（5,15）以产生基带信号的数字进一步的混合级（6,16）和耦合到其它混频级（6,16）的数字式进一步滤波级（7,17），用于通道对基带信号进行选择性滤波。

2. 发明申请

WO2003107612A3 TELECOMMUNICATION SYSTEM WITH SWITCHED TRANSMIT/RECEIVE CHAINS FOR UNCORRELATING CORRELATED NOISE 审中-公开
公开(公告)号：WO2003107612A3
公开(公告)日：2003-12-24
申请号：PCT/IB2003/002301
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , WETZKER, Gunnar
发明人： LEENAERTS, Dominicus, M., W. , WETZKER, Gunnar
IPC分类号： H04B7/06
摘要： Telecommunication systems comprising transmitting units (1) and receiving units (11), with units (1 resp. 11) comprising parallel chains (2-4 resp. 12-14) coupled to processing parts (5 resp. 15), have enhanced data rates / channel capacities, under the assumption that the noise in the chains (2-4 resp. 12-14) is uncorrelated. Correlated noise from external noise sources decreases said rates / capacities. By coupling said chains (2-4 resp. 12-14) to said processing parts (5 resp. 15) via switches (6 resp. 16) for uncorrelating correlated noise in said chains (2-4 resp. 12-14), any correlated noise present in chains (2-4 resp. 12-14) is made uncorrelated. Said switch (30,50,70) (over/sub)samples chain signals, and is further coupled to said processing part (32,52,72) for controlling purposes to switch randomly or programmedly, with said processing part (32,52,72) and said switch (30,50,70) operating synchronically. Said switch (30,50,70) comprises a (de)multiplexer, with a chain comprising at least an antenna (21,22,41,42,61,62) and possibly an amplifier (25,26,43,44) and a mixer (27,28) coupled via said switch (30,50,70) to said processing part (32,52,72) comprising at least a filter (37,57,77), a converter (38,58,78) and a processor (39,59,79) and possibly said mixer (56,76) and said amplifier (75).

3. 发明申请

WO2003107612A2 TELECOMMUNICATION SYSTEM WITH SWITCHED CHAINS FOR UNCORRELATING CORRELATED NOISE 审中-公开
标题翻译：具有用于不相关噪声的切换链路的电信系统
公开(公告)号：WO2003107612A2
公开(公告)日：2003-12-24
申请号：PCT/IB2003/002301
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , WETZKER, Gunnar
发明人： LEENAERTS, Dominicus, M., W. , WETZKER, Gunnar
IPC分类号： H04L25/00
CPC分类号： H04B7/0604 , H04B7/0822 , H04L1/22
摘要： Telecommunication systems comprising transmitting units (1) and receiving units (11), with units (1 resp. 11) comprising parallel chains (2-4 resp. 12-14) coupled to processing parts (5 resp. 15), have enhanced data rates / channel capacities, under the assumption that the noise in the chains (2-4 resp. 12-14) is uncorrelated. Correlated noise from external noise sources decreases said rates / capacities. By coupling said chains (2-4 resp. 12-14) to said processing parts (5 resp. 15) via switches (6 resp. 16) for uncorrelating correlated noise in said chains (2-4 resp. 12-14), any correlated noise present in chains (2-4 resp. 12-14) is made uncorrelated. Said switch (30,50,70) (over/sub)samples chain signals, and is further coupled to said processing part (32,52,72) for controlling purposes to switch randomly or programmedly, with said processing part (32,52,72) and said switch (30,50,70) operating synchronically. Said switch (30,50,70) comprises a (de)multiplexer, with a chain comprising at least an antenna (21,22,41,42,61,62) and possibly an amplifier (25,26,43,44) and a mixer (27,28) coupled via said switch (30,50,70) to said processing part (32,52,72) comprising at least a filter (37,57,77), a converter (38,58,78) and a processor (39,59,79) and possibly said mixer (56,76) and said amplifier (75).
摘要翻译：包括发射单元（1）和接收单元（11）的电信系统具有耦合到处理部分（5或15）的并行链（2-4和12-14）的单元（1和11），具有增强数据速率/通道容量，假设链中的噪声（2-4或12-14）是不相关的。来自外部噪声源的相关噪声降低了所述速率/容量。通过将所述链（2-4或12-14）中的相关噪声不相关的开关（6或16）将所述链（2-4和12-14）耦合到所述处理部分（5和15）链中存在的任何相关噪声（2-4或12-14）都是不相关的。所述开关（30,50,70）（over / sub）采样链信号，并且进一步耦合到所述处理部分（32,52,72），用于控制用所述处理部分（32,52）随机或编程地切换的目的，72）和所述开关（30,50,70）同步工作。所述开关（30,50,70）包括（de）多路复用器，链路至少包括天线（21,22,41,42,61,62）和可能的放大器（25,26,43,44）和经由所述开关（30,50,70）耦合到所述处理部分（32,52,72）的混合器（27,28），至少包括滤波器（37,57,77），转换器（38,58,78） 78）和处理器（39,59,79）以及可能的所述混频器（56,76）和所述放大器（75）。

4. 发明申请

WO2006103587A3 SIGNAL RECEIVER FOR WIDEBAND WIRELESS COMMUNICATION 审中-公开
公开(公告)号：WO2006103587A3
公开(公告)日：2006-10-05
申请号：PCT/IB2006/050827
申请日：2006-03-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , VAN BERKEL, Cornelis, H.
发明人： LEENAERTS, Dominicus, M., W. , VAN BERKEL, Cornelis, H.
IPC分类号： H04B1/28 , H04B1/24 , H04B1/69
摘要： A signal receiver for use in a 60 GHz wireless area network, in which the received RF signal band (100) is converted to a plurality of intermediate frequency (IF) sub-bands (104) and then processing (LPF, AGC, ADC) in the analogue domain of the sub-bands (104) is performed in parallel. As a result, the design requirements of the analogue components are significantly relaxed and it is possible to perform gain control in respect of each sub-band (104), which improves the quality of the received signal.

5. 发明申请

WO2005034358A1 PHASE-SWITCHING DUAL MODULUS PRESCALER 审中-公开
标题翻译：相位切换双模块预分频器
公开(公告)号：WO2005034358A1
公开(公告)日：2005-04-14
申请号：PCT/IB2004/051894
申请日：2004-09-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , MISTRY, Ketan
发明人： LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , MISTRY, Ketan
IPC分类号： H03L7/197
CPC分类号： H03K23/667 , H03K23/662 , H03L7/193
摘要： A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (I p , I n , Q p , Q n ; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (Cl, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs( I p , I n , Q p , Q n ; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.
摘要翻译：提供了具有双模数分频器的相位切换双模预分频器。所述分频器包括第一和第二除以2电路（A; B），其中所述第二分频电路（B）耦合到所述第一分频电路（A）的输出端，并且在至少所述第二分频电路（B）包括每相分开90°的四相输出。提供相位选择单元（PSU），用于选择第二分频电路（B）的四个相位输出（Ip，In，Qp，Qn; INi，INni，INq，Innq）之一。此外，相位控制单元被提供用于向相位选择单元提供控制信号（C1，NC0; C2，NC2; C3，NC3），其中相位选择单元（PSU）执行四相输出（Ip，根据控制信号（C0，NC0; C1，NC1; C2，NC2），输入，Qp，Qn，INi，INni，INq，Innq）。所述相位选择单元（PSU）是基于直接逻辑实现的。基于直接逻辑的相位选择单元的实现能够实现更高的速度并节省芯片上的面积。

6. 发明申请

WO2004055839A1 A PLANAR INDUCTIVE COMPONENT AND AN INTEGRATED CIRCUIT COMPRISING A PLANAR INDUCTIVE COMPONENT 审中-公开
标题翻译：平面电感元件和包含平面电感元件的集成电路
公开(公告)号：WO2004055839A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/005819
申请日：2003-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIEMEIJER, Lukas, F. , HAVENS, Ramon, J. , LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , VEENSTRA, Hugo , VAN DER HEIJDEN, Edwin
发明人： TIEMEIJER, Lukas, F. , HAVENS, Ramon, J. , LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , VEENSTRA, Hugo , VAN DER HEIJDEN, Edwin
IPC分类号： H01F17/00
CPC分类号： H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/367 , H01F2017/008 , H01F2021/125 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a planar inductive component arranged over a substrate (103). The substrate comprises a winding (101) situated in a first plane, a patterned ground shield (102), for shielding the winding (101) from the substrate (103). The winding (101) is at least substantially symmetrical with respect to a mirror plane (104) perpendicular to the first plane. The patterned ground shield (102) comprises a plurality of electrical conductive first tracks (105) situated in a first ground shield plane in parallel with the first plane. The first tracks have an orientation perpendicular to the mirror plane (104). Without the patterned ground shield (102) the winding (101) is capacitively coupled to the substrate (103). The substrate resistance results in a degradation of the quality factor of the inductive component (100). The patterned ground shield (102) shields the winding (101) from the substrate (103), thereby eliminating the degrading effect of the substrate. To prevent a reduction in the effective self inductance of the planar inductive component loop currents have to be prevented in the patterned ground shield, while at the same time transfer of charges induced in the mirrored halves of the winding (100) have to be facilitated. This is achieved by the first tracks (105).
摘要翻译：本发明涉及一种布置在基板（103）上的平面感应元件。衬底包括位于第一平面中的绕组（101），用于屏蔽绕组（101）与衬底（103）的图案化接地屏蔽（102）。绕组（101）相对于垂直于第一平面的镜面（104）至少基本对称。图案化接地屏蔽（102）包括位于与第一平面平行的第一接地屏蔽平面中的多个导电第一轨道（105）。第一轨道具有垂直于镜面（104）的取向。没有图案化的接地屏蔽（102），绕组（101）电容耦合到衬底（103）。基板电阻导致电感元件（100）的品质因数的劣化。图案化的接地屏蔽（102）将绕组（101）与衬底（103）屏蔽，从而消除衬底的劣化作用。为了防止平面感应元件的有效自感的减小，必须在图案化的接地屏蔽中防止环路电流的流动，同时必须促进在绕组（100）的镜像半部中感应的电荷的传输。这通过第一轨道（105）来实现。

7. 发明申请

WO2003049280A1 A LOW NOISE ELECTRONIC CIRCUIT 审中-公开
标题翻译：低噪声电子电路
公开(公告)号：WO2003049280A1
公开(公告)日：2003-06-12
申请号：PCT/IB2002/005024
申请日：2002-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ANNEMA, Anne, J. , LEENAERTS, Dominicus, M., W. , DE VREEDE, Petrus, W., H.
发明人： ANNEMA, Anne, J. , LEENAERTS, Dominicus, M., W. , DE VREEDE, Petrus, W., H.
IPC分类号： H03F1/30
CPC分类号： H03F3/193 , H03F1/301 , H03F2200/294 , H03F2200/372
摘要： An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a common output terminal. The electronic circuit further has a feedback circuit, e.g. in the form of two anti-parallel Field Effect Transistors (M3, M4; M7, M8), connected between the common input terminal and the common output terminal. This feedback circuit has an impedance at radio frequencies which is high-ohmic compared to impedance levels of the two transistors. This ensures a high gain at radio frequencies, and at the same time it can be implemented with only a few components. It also ensures high linearity and a very low current in the feedback circuit, and thus little or no noise is added to the circuit.
摘要翻译：可用作低噪声放大器（LNA）的电子电路包括两个互补场效应晶体管（M1，M2; M5，M6），每个具有栅极，源极和漏极。门作为公共输入端子连接在一起，并且排水口作为公共输出端子连接在一起。电子电路还具有反馈电路，例如，连接在公共输入端子和公共输出端子之间的两个反并联场效应晶体管（M3，M4; M7，M8）的形式。该反馈电路具有与两个晶体管的阻抗水平相比高的欧姆的射频阻抗。这确保了无线电频率的高增益，同时可以仅使用少量组件来实现。它还确保反馈电路中的高线性度和非常低的电流，并且因此很少或没有噪声被添加到电路。

8. 发明申请

WO2006016310A2 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：WO2006016310A2
公开(公告)日：2006-02-16
申请号：PCT/IB2005/052531
申请日：2005-07-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DEKATE, Prashant , LEENAERTS, Dominicus, M., W.
发明人： DEKATE, Prashant , LEENAERTS, Dominicus, M., W.
IPC分类号： H03K23/66
CPC分类号： H03K23/505 , H03K23/662
摘要： A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor.
摘要翻译：提供奇数整数分频因子的分频器包括提供偶数整数分频因子的二进制计数器（10），该分数因子是比奇数分频因子小的第一偶数，二进制计数器具有时钟输入用于接收具有频率的周期性时钟信号（Ck）。该电路还包括耦合到二进制计数器的计数结束电路（20），并且在时钟信号（Ck）的每个偶数整数周期之后的时钟（Ck）周期内产生计数结束信号（EOC），结束的计数信号（EOC）被输入到计数器（10）的输入（IN）。该电路还包括耦合到二进制计数器和时钟信号（Ck）的输出发生器（30），输出发生器（30）产生具有与频率的频率基本相等的频率的输出信号（OUT）信号（Ck）除以奇数分频因子。

9. 发明申请

WO2004042925A1 PLL WITH BALANCED QUADRICORRELATOR 审中-公开
标题翻译： PLL与平衡四分频器
公开(公告)号：WO2004042925A1
公开(公告)日：2004-05-21
申请号：PCT/IB2003/004467
申请日：2003-10-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , LEENAERTS, Dominicus, M., W.
发明人： SANDULEANU, Mihai, A., T. , LEENAERTS, Dominicus, M., W.
IPC分类号： H03L7/085
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/091 , H03L2207/06 , H04L7/0274
摘要： A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).
摘要翻译：一种锁相环（1），包括包括平衡四极管相关器（2）的频率检测器（10），所述环路（1）的特征在于所述四极管相关器（2）包括双边沿时钟双稳态电路（21,22,23 ，24,25,26,27,28）由耦合到多路复用器（31,32,33,34）的信号由与输入D信号（D）具有相同比特率的信号控制。

10. 发明申请

WO2006030342A1 DEVICE FOR ULTRA WIDE BAND FREQUENCY GENERATING 审中-公开
标题翻译：用于超宽带频发生器的设备
公开(公告)号：WO2006030342A1
公开(公告)日：2006-03-23
申请号：PCT/IB2005/052893
申请日：2005-09-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco , LEENAERTS, Dominicus, M., W. , VAN DER WEIDE, Gerard , BERGERVOET, Jozef, R., M.
发明人： VAN DE BEEK, Remco , LEENAERTS, Dominicus, M., W. , VAN DER WEIDE, Gerard , BERGERVOET, Jozef, R., M.
IPC分类号： H03B21/02
CPC分类号： H03D3/009
摘要： Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase / quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase / quadrature oscillation signals and second inphase / quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46). Such frequency selectors (45) comprise multiplexers (126,127) for supplying the second inphase / quadrature oscillation signals, with a combination of these second oscillation signals corresponding with a positive frequency, a negative frequency or a zero frequency, and comprise coders (125) for controlling the multiplexers (126,127).
摘要翻译：用于交换超宽带信号的装置（1）包括用于频率转换信号的频率转换级（20,30）和用于将主相位/正交振荡信号提供给频率转换级（20,30）的振荡级（40）。通过为振荡级（40）提供多相滤波器（43,44）以减少振荡信号中的谐波，主振荡信号将足够清洁。振荡级（40）包括用于将第一同相/正交振荡信号和第二同相/正交振荡信号转换成主振荡信号的混频器（46）。多相过滤器（43,44）可以位于混合器（46）之前和之后。频率选择器（45）代替位于混频器（46）之后的现有技术的多路复用器。这种频率选择器（45）包括用于提供第二同相/正交振荡信号的多路复用器（126,127）以及与正频率，负频率或零频率对应的这些第二振荡信号的组合，并且包括编码器（125），用于控制多路复用器（126,127）。

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