专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017178925A1 CACHE MEMORY ACCESS 审中-公开
标题翻译：高速缓存存取
公开(公告)号：WO2017178925A1
公开(公告)日：2017-10-19
申请号：PCT/IB2017/051944
申请日：2017-04-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： WILLIAMS, Derek , GUTHRIE, Guy , JACKSON, Jonathan, Robert , STARKE, William , STUECHELI, Jeffrey
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F12/0842 , G06F12/0893 , G06F2212/1024 , G06F2212/6042 , G06F2212/621
摘要： A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a system wide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the system wide coherence response for the memory access request. In response to the early indication and prior to receiving the system wide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.
摘要翻译：多处理器数据处理系统包括支持多个处理器核的多个垂直高速缓存分层结构，系统存储器和系统互连。响应于来自第一处理器核心的加载和保留请求，支持第一处理器核心的第一高速缓存存储器在系统互连上发出用于加载和保留请求的目标高速缓存行的存储器访问请求。响应于存储器访问请求并且在接收对于存储器访问请求的系统范围的一致性响应之前，第一高速缓冲存储器通过高速缓存到高速缓存干预从第二垂直高速缓存层级中的第二高速缓冲存储器接收目标高速缓存行和尽早指示存储器访问请求的系统范围内一致性响应。响应于早期指示并且在接收系统范围一致性响应之前，第一高速缓冲存储器发起处理以更新第一高速缓冲存储器中的目标高速缓存行。

2. 发明申请

WO2013118008A1 PROCESSOR PERFORMANCE IMPROVEMENT FOR INSTRUCTION SEQUENCES THAT INCLUDE BARRIER INSTRUCTIONS 审中-公开
标题翻译：包括障碍指示的指令序列的处理器性能改进
公开(公告)号：WO2013118008A1
公开(公告)日：2013-08-15
申请号：PCT/IB2013/050538
申请日：2013-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： WILLIAMS, Derek, Edward , GUTHRIE, Guy, Lynn , STARKE, William
IPC分类号： G06F9/00
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F12/0831
摘要： A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.
摘要翻译：一种用于处理包括屏障指令，屏障指令之前的加载指令以及跟随障碍指令之后的后续存储器访问指令的指令序列的技术包括：通过处理器核心确定加载指令基于处理器核心最早是对应于加载指令的读取操作和用于加载指令的数据的良好组合响应。该技术还包括如果在完成屏障指令之前没有启动后续存储器访问指令的执行，则响应于确定完成的屏障指令，由处理器核心启动后续存储器访问指令的执行。该技术还包括如果在完成屏障指令之前启动后续存储器访问指令的执行，则响应于确定所完成的屏障指令，处理器核心中断，跟踪关于无效的后续存储器访问指令。

3. 发明申请

WO2022034407A1 MULTIFUNCTION COMMUNICATION INTERFACE SUPPORTING MEMORY SHARING AMONG DATA PROCESSING SYSTEMS 审中-公开
公开(公告)号：WO2022034407A1
公开(公告)日：2022-02-17
申请号：PCT/IB2021/056733
申请日：2021-07-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： SIEGEL, Michael , STARKE, William , STUECHELI, Jeffrey , ARIMILLI, Lakshminarayana , VALK, Kenneth , MIKOS, James , KROLAK, David
IPC分类号： G06F11/30
摘要： In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifiesa memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

4. 发明申请

WO2018100478A1 MANAGING LOWEST POINT OF COHERENCY (LPC) MEMORY USING SERVICE LAYER ADAPTER 审中-公开
公开(公告)号：WO2018100478A1
公开(公告)日：2018-06-07
申请号：PCT/IB2017/057408
申请日：2017-11-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： ARIMILLI, Lakshminarayana, Baba , STARKE, William , STUECHELI, Jeffrey , BENJAMINI, Yiftach , BLANER, Bartholomew , ADAR, Etai
IPC分类号： G06F13/28
摘要： Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

5. 发明申请

WO2014083442A1 COHERENT PROXY FOR ATTACHED PROCESSOR 审中-公开
标题翻译：附件处理器的相关代码
公开(公告)号：WO2014083442A1
公开(公告)日：2014-06-05
申请号：PCT/IB2013/058917
申请日：2013-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： STUECHELI, Jeffrey , SIEGEL, Michael, Steven , BLANER, Bartholomew , MARINO, Charles, Francis , STARKE, William
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/622
摘要： A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.
摘要翻译：主相干系统的相干连接处理器代理（CAPP）相对于AP的高速缓冲存储器接收来自附加处理器（AP）的存储器访问请求和存储器访问请求的目标地址的预期相干状态。作为响应，CAPP确定目标地址的相干状态以及预期状态是否与所确定的相干状态相匹配。响应于确定预期状态与确定的相干状态匹配，CAPP发出与在主要相干系统的系统结构上从AP接收的存储器访问请求相对应的存储器访问请求。响应于确定预期状态与由CAPP确定的相干状态不匹配，CAPP向AP发送故障消息，而不在系统结构上发出与从AP接收到的对应的存储器访问请求。

6. 发明申请

WO2011076599A1 AGGREGATE SYMMETRIC MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：聚合对称多处理器系统
公开(公告)号：WO2011076599A1
公开(公告)日：2011-06-30
申请号：PCT/EP2010/069482
申请日：2010-12-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , STARKE, William , GUTHRIE, Guy, Lynn , WILLIAMS, Derek, Edward , MARINO, Charles, Francis
发明人： STARKE, William , GUTHRIE, Guy, Lynn , WILLIAMS, Derek, Edward , MARINO, Charles, Francis
IPC分类号： G06F12/02 , G06F12/08 , G06F15/80
CPC分类号： G06F12/0284 , G06F12/084 , G06F12/0842
摘要： An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.
摘要翻译：聚合对称多处理器（SMP）数据处理系统包括包括至少第一和第二处理单元的第一SMP计算机和包括至少第三和第四处理单元以及第二和第三系统存储器池的第一系统存储器池和第二SMP计算机。第二系统存储器池是第四处理单元不可访问的受限访问存储器池，并且可被至少第二和第三处理单元访问，并且第三系统存储池可由第三处理单元和第四处理单元访问。互连耦合第一SMP计算机中的第二处理单元，用于对第二SMP计算机中的第二系统存储池进行加载存储一致的有序访问，使得第一SMP计算机中的第二处理单元和第二系统存储器池第二台SMP计算机形成了合成的第三台SMP计算机。

7. 发明申请

WO2015004579A1 VIRTUAL MACHINE BACKUP 审中-公开
标题翻译：虚拟机备份
公开(公告)号：WO2015004579A1
公开(公告)日：2015-01-15
申请号：PCT/IB2014/062822
申请日：2014-07-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： NORTH, Geraint , STARKE, William , GUTHRIE, Guy, Lynn , WILLIAMS, Phillip , SHEN, Hugh , NAYAR, Naresh
IPC分类号： G06F11/20 , G06F9/46
CPC分类号： G06F11/1451 , G06F3/0619 , G06F3/065 , G06F3/0652 , G06F3/0685 , G06F9/45558 , G06F11/1438 , G06F11/1484 , G06F11/2023 , G06F11/2097 , G06F12/0804 , G06F12/0806 , G06F12/0875 , G06F12/0891 , G06F12/109 , G06F12/12 , G06F2009/45583 , G06F2009/45591 , G06F2201/885 , G06F2212/1032 , G06F2212/152 , G06F2212/281 , G06F2212/313 , G06F2212/60 , G06F2212/608
摘要： A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
摘要翻译：计算机系统包括处理器单元，该处理器单元被布置成运行运行一个或多个虚拟机的管理程序; 连接到处理器单元并且包括多个高速缓存行的高速缓存，每个高速缓存行包括存储器地址，高速缓存行和图像修改标志; 以及连接到高速缓存并且被布置为存储至少一个虚拟机的图像的存储器。处理器单元被布置成在存储器中定义日志，并且高速缓存进一步包括高速缓存控制器，该高速缓存控制器被设置成为由正在备份的虚拟机修改的高速缓存行设置图像修改标志，但不设置用于由管理程序修改的高速缓存行在特权模式下运行; 定期检查图像修改标志; 并在定义的日志中只写入标记的缓存行的内存地址。

8. 发明申请

WO2015004575A1 VIRTUAL MACHINE BACKUP 审中-公开
标题翻译：虚拟机备份
公开(公告)号：WO2015004575A1
公开(公告)日：2015-01-15
申请号：PCT/IB2014/062791
申请日：2014-07-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： NORTH, Geraint , STARKE, William , GUTHRIE, Guy, Lynn , WILLIAMS, Phillip , SHEN, Hugh , NAYAR, Naresh
IPC分类号： G06F11/20 , G06F9/46
CPC分类号： G06F11/1451 , G06F9/45533 , G06F9/45558 , G06F11/1438 , G06F11/1458 , G06F11/1484 , G06F12/0804 , G06F12/0842 , G06F12/0891 , G06F12/0895 , G06F2009/45583 , G06F2201/805 , G06F2201/815 , G06F2201/885 , G06F2212/1016 , G06F2212/1032 , G06F2212/1044 , G06F2212/152 , G06F2212/60
摘要： A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
摘要翻译：计算机系统包括处理器单元，其被配置为运行运行一个或多个虚拟机的管理程序; 连接到所述处理器单元并且包括多个高速缓存行的高速缓存，每个高速缓存行包括存储器地址，高速缓存行和图像修改标志; 以及连接到高速缓存并被布置成存储至少一个虚拟机的图像的存储器。处理器单元被布置为在存储器中定义日志，并且高速缓存还包括高速缓存控制器，该高速缓存控制器被布置为为被备份的虚拟机修改的高速缓存行设置图像修改标志，但不对于由管理程序修改的高速缓存线在特权模式下运行; 定期检查图像修改标志; 并且只写入定义的日志中标记的高速缓存行的内存地址。

9. 发明申请

WO2023006383A1 MEMORY MIGRATION WITHIN A MULTI-HOST DATA PROCESSING ENVIRONMENT 审中-公开
公开(公告)号：WO2023006383A1
公开(公告)日：2023-02-02
申请号：PCT/EP2022/069086
申请日：2022-07-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： WILLIAMS, Derek , GUTHRIE, Guy , STARKE, William , STUECHEL, Jeffrey
IPC分类号： G06F3/06 , G06F9/455 , G06F9/50
摘要： A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.

10. 发明申请

WO2023031016A1 HIERARCHICAL RING-BASED INTERCONNECTION NETWORK FOR SYMMETRIC MULTIPROCESSORS 审中-公开
公开(公告)号：WO2023031016A1
公开(公告)日：2023-03-09
申请号：PCT/EP2022/073700
申请日：2022-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： MARINO, Charles , STARKE, William , REDDY, Praveen , HOLLAWAY, John, Jr. , HOWE, Daniel C , KROLAK, David
IPC分类号： G06F13/37 , H04L12/433 , H04L12/417 , G06F15/173 , H04L47/215 , H04L43/0876 , G06F12/0831
摘要： A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses (140, 150, 160) comprised on the symmetric multiprocessor, wherein each of the buses (140, 150, 160) are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses (140, 150, 160) to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network (140, 150, 160) configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式