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1. 发明申请

WO2016142433A1 SENSOR ARRANGEMENT FOR POSITION SENSING 审中-公开
标题翻译：传感器布置用于位置感测
公开(公告)号：WO2016142433A1
公开(公告)日：2016-09-15
申请号：PCT/EP2016/055052
申请日：2016-03-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM RESEARCH GMBH
发明人： HAEBERLE, Walter , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G01V3/08 , G01R33/09 , A61B5/06
CPC分类号： G01D5/16 , G01B7/14 , G01R33/09 , G01V3/081
摘要： A sensor arrangement for position sensing comprises a first magnetoresistive element (1) and a second magnetoresistive element (2). A magnetic field source (3) provides a magnetic field with a first magnetic pole (N) and a second magnetic pole (S). The magnetic field source (3) is arranged between the first magnetoresistive element (1) and the second magnetoresistive element (2) with the first magnetic pole (N) facing the first magnetoresistive element (1) and the second magnetic pole (S) facing the second magnetoresistive element (2). The first magnetoresistive element (1) is arranged in the magnetic field and provides a first output signal (R1) dependent on a position of the first magnetoresistive element (1) relative to the magnetic field source (3). The second magnetoresistive element (2) is arranged in the magnetic field and provides a second output signal (R2) dependent on a position of the second magnetoresistive element (2) relative to the magnetic field source (3). A measurement unit is configured to determine a position of the magnetic field source (3) relative to the first and the second magnetoresistive elements (1, 2) dependent on the first output signal (R1) and the second output signal (R2).
摘要翻译：用于位置检测的传感器装置包括第一磁阻元件（1）和第二磁阻元件（2）。磁场源（3）提供与第一磁极（N）和第二磁极（S）的磁场。磁场源（3）被布置在第一磁阻元件（1）和第二磁阻元件（2）之间，第一磁极（N）面对第一磁阻元件（1）和第二磁极（S）第二磁阻元件（2）。第一磁阻元件（1）被布置在磁场中，并且提供取决于第一磁阻元件（1）相对于磁场源（3）的位置的第一输出信号（R1）。第二磁阻元件（2）被布置在磁场中并且提供取决于第二磁阻元件（2）相对于磁场源（3）的位置的第二输出信号（R2）。测量单元被配置为根据第一输出信号（R1）和第二输出信号（R2）确定磁场源（3）相对于第一和第二磁阻元件（1,2）的位置。

2. 发明申请

WO2016067139A1 NEUROMORPHIC SYNAPSES 审中-公开
标题翻译：神经突触
公开(公告)号：WO2016067139A1
公开(公告)日：2016-05-06
申请号：PCT/IB2015/057824
申请日：2015-10-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM RESEARCH GMBH
发明人： ELEFTHERIOU, Evangelos Stavros , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G06N3/10
CPC分类号： G06N3/049 , G06N3/063 , G06N3/088
摘要： A neuromorphic synapse (11) comprises a resistive memory cell (15) connected in circuitry having first and second input terminals (21,22).These input terminals (21,22) respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry also has an output terminal (23) for providing a synaptic output signal which is dependent on resistance of the memory cell (15).The circuitry is operable such that the synaptic output signal is provided at the output terminal (23) in response to application at the first input terminal (21) of the read portion of the pre-neuron action signal,and such that a programming signal,for programming resistance of the memory cell (15), is applied to the cell (15) in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals (21,22) respectively. The synapse (11) can be adapted for operation with identical pre-neuron and post-neuron action signals.
摘要翻译：神经突触（11）包括在具有第一和第二输入端子（21,22）的电路中连接的电阻性存储单元（15）。这些输入端子（21,22）分别接收预神经元和神经元后神经元动作信号，每个具有读取部分和写入部分。电路还具有用于提供取决于存储器单元（15）的电阻的突触输出信号的输出端子（23）。该电路可操作使得突触输出信号在输出端（23）处被响应地提供以应用于前神经元动作信号的读取部分的第一输入端（21），并且使得用于编程存储单元（15）的电阻的编程信号作为响应应用于单元（15）分别在第一和第二输入端子（21,22）处同时应用神经元前神经元和后神经元作用信号的写入部分。突触（11）可以适应于具有相同的前神经元和神经元后动作信号的操作。

3. 发明申请

WO2017163139A1 ARTIFICIAL NEURON APPARATUS 审中-公开
标题翻译：人工神经元装置
公开(公告)号：WO2017163139A1
公开(公告)日：2017-09-28
申请号：PCT/IB2017/051081
申请日：2017-02-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM RESEARCH GMBH
发明人： ELEFTHERIOU, Evangelos , KULL, Lukas , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas , STANISAVLJEVIC, Milos
IPC分类号： G06N3/02
CPC分类号： G06N3/0635 , G06N3/049
摘要： Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.
摘要翻译：人造神经元装置包括连接在具有神经元输入的输入电路中的电阻式存储器单元，用于接收神经元输入信号，以及用于将读取电流提供给单元的电流源。响应于一组控制信号，输入电路可选择性地配置，定义交替的读取和写入操作阶段，在读取阶段期间将读取电流施加到单元并将编程电流施加到单元，以编程单元电阻在写入阶段期间收到神经元输入信号。响应于连续的神经元输入信号，单元电阻从第一状态逐渐变为第二状态。该装置还包括输出电路，该输出电路包括神经元输出端和数字锁存器，数字锁存器连接到输入电路，用于接收取决于单元电阻的测量信号。

4. 发明申请

WO2014083460A1 POSITION SENSOR 审中-公开
标题翻译：位置传感器
公开(公告)号：WO2014083460A1
公开(公告)日：2014-06-05
申请号：PCT/IB2013/060002
申请日：2013-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM JAPAN, LTD. , IBM RESEARCH GMBH
发明人： HAEBERLE, Walter , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G01B7/00
CPC分类号： G01D5/16 , G01D5/145 , G01R33/09
摘要： A position sensor comprises a magnetoresistive element (1). The magnetoresistive element (1) comprises a stack (11) of layers including at least a conductive layer (112) in between two magnetic layers (111,113). The layers have a longitudinal extension (L) along a longitudinal axis (X) and a lateral extension along a transverse axis (Y). A magnet (2) is provided comprising a magnetic dipole (N/S) with a dipole axis (DA) orthogonal to a plane defined by the longitudinal axis (X) and the transverse axis (Y). The electrical resistance of the conductive layer (112) depends on a position of the magnet (2) along the longitudinal axis (X). The position sensor provides for nano-scale sensing.
摘要翻译：位置传感器包括磁阻元件（1）。磁阻元件（1）包括在两个磁性层（111,113）之间至少包括导电层（112）的层叠层（11）。这些层沿着纵向轴线（X）具有纵向延伸（L）和沿横向轴线（Y）的横向延伸。提供一种磁体（2），其包括与由纵轴（X）和横轴（Y）限定的平面正交的偶极轴（DA）的磁偶极子（N / S）。导电层（112）的电阻取决于磁体（2）沿纵向轴线（X）的位置。位置传感器提供纳米级感测。

5. 发明申请

WO2017001956A1 NEUROMORPHIC PROCESSING DEVICES 审中-公开
标题翻译：神经处理装置
公开(公告)号：WO2017001956A1
公开(公告)日：2017-01-05
申请号：PCT/IB2016/053353
申请日：2016-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM RESEARCH GMBH
发明人： ELEFTHERIOU, Evangelos Stavros , LE GALLO, Manuel , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G06N3/04
CPC分类号： G06N3/0635 , G06N3/049
摘要： A neuromorphic processing device (1) has a device input (2), for receiving an input data signal, and an assemblage of neuron circuits (3). Each neuron circuit (3) comprises a resistive memory cell (14) which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals (11) for programming cell resistance to vary the neuron state, and a neuron output circuit (15) for supplying a neuron output signals (12) in response to cell resistance traversing a threshold. The device (1) includes an input signal generator (4) connected to the device input (2) and the assemblage of neuron circuits (3), for generating neuron input signals (11) for the assemblage in dependence on the input data signal. The device (1) further includes a device output circuit (5), connected to neuron output circuits (15) of the assemblage, for producing a device output signal dependent on neuron output signals (12) of the assemblage, whereby the processing device (1) exploits stochasticity of resistive memory cells of the assemblage.
摘要翻译：神经形态处理装置（1）具有用于接收输入数据信号的装置输入（2）和神经元电路（3）的组合。每个神经元电路（3）包括电阻存储器单元（14），其被布置为存储由单元电阻指示的神经元状态，并且接收用于编程单元电阻以改变神经元状态的神经元输入信号（11），以及神经元输出电路（15），用于响应于穿过阈值的单元电阻提供神经元输出信号（12）。设备（1）包括连接到设备输入（2）的输入信号发生器（4）和神经元电路（3）的组合，用于根据输入数据信号产生用于组合的神经元输入信号（11）。装置（1）还包括与装置的神经元输出电路（15）连接的装置输出电路（5），用于根据装置的神经元输出信号（12）产生装置输出信号，由此处理装置 1）利用组合的电阻记忆单元的随机性。

6. 发明申请

WO2016146468A1 NEUROMORPHIC SYNAPSES 审中-公开
标题翻译：神经传播
公开(公告)号：WO2016146468A1
公开(公告)日：2016-09-22
申请号：PCT/EP2016/055098
申请日：2016-03-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM RESEARCH GMBH
发明人： ELEFTHERIOU, Evangelos Stavros , LE GALLO, Manuel , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G06N3/04 , G06N3/063 , G11C11/54
CPC分类号： G06N3/0635 , G06N3/049 , G06N3/063 , G06N3/08 , G11C11/54 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： Neuromorphic synapse apparatus (11) comprises a memelement (20) for storing a synaptic weight, and programming logic (21). The memelement (20) is adapted to exhibit a desired programming characteristic. The programming logic (21) isresponsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement (20) to update said weight. The programming logic (21) may be responsive to an input signal indicating an input weight-change value ΔW i , and may be adapted to generate a programming signal dependent on the input weight-change value ΔW i .The programming logic (21) is adapted such that the programming signals exploit the programming characteristic of the memelement (20) to provide a desired weight-dependent synaptic update efficacy.
摘要翻译：神经突触装置（11）包括用于存储突触重量的记忆元件（20）和编程逻辑（21）。元件（20）适于表现出期望的编程特性。编程逻辑（21）响应促进突触权重的更新的响应，用于产生编程信号，用于对所述元件（20）进行编程以更新所述权重。编程逻辑（21）可以响应于指示输入权重变化值ΔWi的输入信号，并且可以适于产生取决于输入权重变化值ΔWi的编程信号。编程逻辑（21）被适配为所述编程信号利用所述元件（20）的编程特性以提供期望的与权重相关的突触更新效能。

7. 发明申请

WO2022101725A1 MULTI-TERMINAL NEUROMORPHIC DEVICE 审中-公开
公开(公告)号：WO2022101725A1
公开(公告)日：2022-05-19
申请号：PCT/IB2021/059858
申请日：2021-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
发明人： SYED, Ghazi Sarwat , SEBASTIAN, Abu , MORAITIS, Timoleon , KERSTING, Benedikt
IPC分类号： G06N3/063
摘要： A neuromorphic memory element (100,200,300,706) comprises a memristor, a plurality of the neuromrophic memory elements (100,200,300,706) and a method for operating the same may be provided. The memristor comprises an input signal terminal (104), an output signal terminal (106), and a control signal terminal, and a memristive active channel (108) comprising a phase change material. The memristive active channel (108) extends longitudinal between the input signal terminal (104) and the output signal terminal (106), and a control signal voltage at the control signal terminal is configured to represent volatile biological neural processes of the neuromorphic memory element (100,200,300,706), and a bias voltage between the input signal terminal (104) and the output terminal (106) is configured to represent non-volatile biological processes of the neuromorphic memory element (100,200,300,706).

8. 发明申请

WO2021018731A1 LEARNING AND RECALL IN SPIKING NEURAL NETWORKS 审中-公开
公开(公告)号：WO2021018731A1
公开(公告)日：2021-02-04
申请号：PCT/EP2020/070821
申请日：2020-07-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： CHERUBINI, Giovanni , SEBASTIAN, Abu
IPC分类号： G06N3/04 , G06N3/08
摘要： Methods and apparatus are provided for memorizing data signals in a spiking neural network. For each data signal, such a method includes supplying metadata relating to the data signal to a machine learning model trained to generate an output signal, indicating a relevance class for a data signal, from input metadata for that data signal. The method includes iteratively supplying the data signal to a sub-assembly of neurons, interconnected via synaptic weights, of a spiking neural network and training the synaptic weights to memorize the data signal in the sub-assembly. The method further comprises assigning neurons of the network to the sub-assembly in dependence on the output signal of the model such that more relevant data signals are memorized by larger sub-assemblies. The data signal memorized by a sub-assembly can be subsequently recalled by activating neurons of that sub-assembly.

9. 发明申请

WO2021008868A1 A METHOD FOR INTERFACING WITH HARDWARE ACCELERATORS 审中-公开
公开(公告)号：WO2021008868A1
公开(公告)日：2021-01-21
申请号：PCT/EP2020/068377
申请日：2020-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： PIVETEAU, Christophe , IOANNOU, Nikolas , KRAWCZUK, Igor , LE GALLO-BOURDEAU, Manuel , SEBASTIAN, Abu , ELEFTHERIOU, Evangelos, Stavros
IPC分类号： G06F9/48 , G06N3/04 , G06N3/08
摘要： The present disclosure relates to a method for executing a computation task composed of at least one set of operations where subsets of pipelineable operations of the set of operations are determined in accordance with a pipelining scheme. A single routine may be created for enabling execution of the determined subsets of operations by a hardware accelerator. The routine has, as arguments, a value indicative of input data and values of configuration parameters of the computation task, where a call of the routine causes a scheduling of the subsets of operations on the hardware accelerator in accordance with the values of the configuration parameters. Upon receiving input data of the computation task, the routine may be called to cause the hardware accelerator to perform by the computation task in accordance with the scheduling.

10. 发明申请

WO2022101741A1 DRIFT AND NOISE CORRECTED MEMRISTIVE DEVICE 审中-公开
公开(公告)号：WO2022101741A1
公开(公告)日：2022-05-19
申请号：PCT/IB2021/060194
申请日：2021-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM ISRAEL - SCIENCE & TECHNOLOGY LTD.
发明人： SYED, Ghazi Sarwat , KERSTING, Benedikt , SEBASTIAN, Abu
IPC分类号： G01C13/00
摘要： A memristor memory device(100) comprises a memristive memory cell(102), an input terminal(104), an output terminal(108), and a gate terminal(112). The input terminal(104) and the output terminal(108) are directly attached to the memristive memory cell(102), and the gate terminal(112) is electrically isolated from the memristive memory cell(102). The gate terminal(112) is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell(102), by which a correction of non-ideal conductance modulations of the memristor memory device(100) is achieved.

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