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1. 发明申请

WO2016113643A1 NEUROMORPHIC MEMORY CIRCUIT 审中-公开
标题翻译：神经元存储器电路
公开(公告)号：WO2016113643A1
公开(公告)日：2016-07-21
申请号：PCT/IB2016/050035
申请日：2016-01-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： KIM, SangBum , LAM, Chung, Hon
IPC分类号： G06N3/063
CPC分类号： G11C11/54 , G06N3/049 , G06N3/063 , G06N3/088 , G11C11/5678 , G11C13/0002 , G11C13/0004
摘要： A neuromorphic memory circuit (102) includes a programmable resistive memory element (108), an axon LIF line (116) to transmit an axon LIF pulse, and a dendrite LIF line (110) to build up a dendrite LIF charge over time. A first transistor (104) provides a discharge path for the dendrite LIF charge through the programmable resistive memory element (108) when the axon LIF line (116) transmits the axon LIF pulse. An axon STDP line (122) transmits an axon STDP pulse. The axon STDP pulse is longer than the axon LIF pulse. A dendrite STDP line (118) is configured to transmit a dendrite STDP pulse after voltage (V post ) at the dendrite LIF line (110) falls below a threshold voltage (120). A second transistor (106) is coupled to the axon STDP line (122) and the programmable resistive memory element (108). The second transistor (106) provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element (108) when the axon STDP line (122) transmits the axon STDP pulse.
摘要翻译：神经形态记忆电路（102）包括可编程电阻性存储器元件（108），用于透射轴突LIF脉冲的轴突LIF线（116）和枝晶LIF线（110），以随时间建立枝晶LIF电荷。当轴突LIF线（116）透射轴突LIF脉冲时，第一晶体管（104）通过可编程电阻性存储元件（108）提供用于枝晶LIF电荷的放电路径。轴突STDP线（122）发送轴突STDP脉冲。轴突STDP脉冲长于轴突LIF脉冲。枝晶STDP线（118）被配置为在枝晶LIF线（110）处的电压（V post）之后传输树突STDP脉冲低于阈值电压（120）。第二晶体管（106）耦合到轴突STDP线（122）和可编程电阻性存储元件（108）。当轴突STDP线（122）透射轴突STDP脉冲时，第二晶体管（106）提供用于通过可编程电阻性存储元件（108）的枝晶STDP脉冲的电路径。

2. 发明申请

WO2022268416A1 PULSING SYNAPTIC DEVICES BASED ON PHASE-CHANGE MEMORY TO INCREASE THE LINEARITY IN WEIGHT UPDATE 审中-公开
公开(公告)号：WO2022268416A1
公开(公告)日：2022-12-29
申请号：PCT/EP2022/063616
申请日：2022-05-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： CARTER, Fabia , BRIGHTSKY, Matthew Joseph , KIM, Wanki , BOUVIER, Maxence , KIM, SangBum
IPC分类号： G11C11/54 , G11C13/00 , G06N3/061 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2013/0092 , G11C2213/79
摘要： According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to amorphize the phase change material of the PCM cell; responsive to applying the RESET pulse, applying an incubation pulse to the PCM cell; and applying a plurality of partial SET pulses to incrementally increase the conductance of the PCM cell.

3. 发明申请

WO2014089125A1 THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME 审中-公开
标题翻译：三维存储阵列和操作方案
公开(公告)号：WO2014089125A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/072939
申请日：2013-12-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： KIM, SangBum , LAM, Chung H.
IPC分类号： H01L27/10
CPC分类号： G11C13/0004 , G11C7/18 , G11C11/21 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226
摘要： A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers.
摘要翻译：一种用于操作三维存储器阵列的系统，方法和计算机程序产品。示例性阵列包括具有第一，第二和栅极端子的存取晶体管。位线耦合到第一端子，耦合到栅极端子的字线和垂直线耦合到第二端子。位，字和垂直线彼此垂直。存储单元沿着垂直线定位，包括与存储元件串联耦合的双向访问设备。通过施加彼此极性相反的第一和第二写入电压，存储元件可编程为第一和第二状态。阵列包括平行于字和位线的导电板，并垂直于垂直线。导电板与相同高度的存储单元耦合，并由绝缘层隔开。

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