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1. 发明申请

WO2009062066A2 METHOD AND APPARATUS FOR COMBINED MEDIUM ACCESS CONTROL AND RADIO LINK CONTROL PROCESSING 审中-公开
标题翻译：用于组合中访问控制和无线链路控制处理的方法和装置
公开(公告)号：WO2009062066A2
公开(公告)日：2009-05-14
申请号：PCT/US2008/082844
申请日：2008-11-07
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , PRAGADA, Ravikumar V. , HEPLER, Edward, L. , GAUVREAU, Jean-Louis , MARINIER, Paul , DAVIS, Jeffrey T. , WANG, Shiehlie T.
发明人： PRAGADA, Ravikumar V. , HEPLER, Edward, L. , GAUVREAU, Jean-Louis , MARINIER, Paul , DAVIS, Jeffrey T. , WANG, Shiehlie T.
IPC分类号： H04W80/00
CPC分类号： H04W28/06 , H04L49/90 , H04L49/901 , H04L69/12 , H04W80/02 , H04W88/02
摘要： A method and apparatus for combined medium access control (MAC) and radio link control (RLC) processing are disclosed. For uplink processing, a combined MAC/RLC (CMR) entity generates an SDU descriptor and allocates protocol data unit (PDU) descriptor resources. A protocol engine (PE) populates a PDU descriptor for each PDU carrying at least a portion of the SDU and generates a MAC PDU in a physical layer shared memory based on the SDU descriptor and the PDU descriptor. The MAC PDU is generated while moving RLC SDU data from the bulk memory to the physical layer shared memory. For downlink processing, received MAC PDUs are stored in the physical layer shared memory. The PE reads MAC and RLC headers in the MAC PDU and populates an SDU segment descriptor (SD) and corresponding PDU descriptors for each SDU segment. The CMR entity merges SDU SDs that comprise a same RLC SDU.
摘要翻译：公开了一种用于组合介质访问控制（MAC）和无线电链路控制（RLC）处理的方法和装置。对于上行链路处理，组合MAC / RLC（CMR）实体生成SDU描述符并分配协议数据单元（PDU）描述符资源。协议引擎（PE）为携带至少一部分SDU的每个PDU填充PDU描述符，并且基于SDU描述符和PDU描述符在物理层共享存储器中生成MAC PDU。在将RLC SDU数据从大容量存储器移动到物理层共享存储器的同时产生MAC PDU。对于下行链路处理，接收到的MAC PDU被存储在物理层共享存储器中。 PE读取MAC PDU中的MAC和RLC头，并为每个SDU段填充SDU段描述符（SD）和相应的PDU描述符。 CMR实体合并构成相同RLC SDU的SDU SD。

2. 发明申请

WO2013025534A1 METHODS AND SYSTEMS FOR PACKET DIFFERENTIATION 审中-公开
标题翻译：分组差异的方法和系统
公开(公告)号：WO2013025534A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/050405
申请日：2012-08-10
申请人： VID SCALE, INC. , MA, Liangping , ZIERA, Ariela , SHAHEEN, Kamel, M. , LIU, Hang , DENG, Zhuorong , LIU, Weimin , WALLACE, Chris , RAPAPORT, Avi , CHEN, Zhifeng , HEPLER, Edward, L. , MILLER, James, M. , PRAGADA, Ravikumar, V. , RYU, Eun
发明人： MA, Liangping , ZIERA, Ariela , SHAHEEN, Kamel, M. , LIU, Hang , DENG, Zhuorong , LIU, Weimin , WALLACE, Chris , RAPAPORT, Avi , CHEN, Zhifeng , HEPLER, Edward, L. , MILLER, James, M. , PRAGADA, Ravikumar, V. , RYU, Eun
IPC分类号： H04L12/56
CPC分类号： H04N19/66 , H04L47/20 , H04L47/2408 , H04L47/34 , H04L47/624 , H04L49/3009 , H04L65/4053 , H04L65/602 , H04L65/80 , H04W4/18 , H04W28/065
摘要： Methods and systems are disclosed facilitate differentiated QoS service for packets within a single packet stream. For example, extended QCI values may be used to differentiate service of video packets associated with different priorities. A flexible representation of QoS requirements/parameters is disclosed where QoS may be defined as a hyperspace that is a function of base QoS parameters. A WTRU may explicitly specify and/or request desired QoS parameters. A WTRU may be configured to perform one or more of video packet separation into a plurality of video packet sub-streams, merging of the video packet sub-streams, and/or reordering of the packets included in the video packet sub-streams. Techniques may be utilized to exposing more information to a data transmission network regarding the type of video packets (and/or other packets) being transmitted.
摘要翻译：公开的方法和系统有助于在单个分组流内的分组的差分QoS服务。例如，可以使用扩展QCI值来区分与不同优先级相关联的视频分组的服务。公开了QoS要求/参数的灵活表示，其中QoS可以被定义为作为基本QoS参数的函数的超空间。 WTRU可以明确地指定和/或请求所需的QoS参数。 WTRU可以被配置为执行视频分组分离成多个视频分组子流中的一个或多个，视频分组子流的合并和/或包括在视频分组子流中的分组的重新排序。可以使用技术来向数据传输网络发送关于正被发送的视频分组（和/或其他分组）的类型的更多信息。

3. 发明申请

WO2004077722A2 COMPONENTS AND METHODS FOR PROCESSING WIRELESS COMMUNICATION DATA IN PRESENCE OF FORMAT UNCERTAINTY 审中-公开
标题翻译：处理格式不确定性无线通信数据的组件和方法
公开(公告)号：WO2004077722A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/004658
申请日：2004-02-18
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , REZNIK, Alexander , HEPLER, Edward, L.
发明人： REZNIK, Alexander , HEPLER, Edward, L.
IPC分类号： H04L
CPC分类号： H04L1/1829 , H04B1/707 , H04L1/0006 , H04L1/0025 , H04L1/0032 , H04L1/0071
摘要： Components and method are provided to efficiently process wireless communications data where prior knowledge of the specific format of the communication data is not available. A wireless transmit receive unit (WTRU) is configured for use in a wireless communication system where communication data for selected channels is transmitted in system time frames in formats selected from among a set of predefined formats. The WTRU has a receiver, a memory, a received chip rate processor (RCRP), a format detector and a de-interleaver. The RCRP is preferably configured to despread each wireless signal of spread data received in each time frame using a minimum spreading code or other appropriate key sequence and to store resultant despread data for each respective time frame in the memory. The format detector is preferably configured to determine the number of physical channels and the respective spreading factor for each physical channel for the wireless signal of spread data received in each time frame. The de-interleaver is preferably configured to de-interleave the stored data despread by the RCRP for each respective time frame into the number of physical channels determined by the format detector for the respective time frame.
摘要翻译：提供组件和方法以有效地处理无线通信数据，其中通信数据的特定格式的先前知识不可用。无线发射接收单元（WTRU）被配置为在无线通信系统中使用，其中所选信道的通信数据以系统时间帧的形式从一组预定格式中选择。 WTRU具有接收机，存储器，接收的码片速率处理器（RCRP），格式检测器和解交织器。优选地，RCRP被配置为使用最小扩展码或其他适当的密钥序列来解扩每个时间帧中接收的扩展数据的每个无线信号，并且将每个相应时间帧的合成解扩数据存储在存储器中。格式检测器优选地被配置为确定在每个时间帧中接收的扩展数据的无线信号的物理信道的数量和每个物理信道的相应扩展因子。解交织器优选地被配置为将用于每个相应时间帧的由RCRP解扩的存储的数据解交织成由各个时间帧由格式检测器确定的物理信道的数量。

4. 发明申请

WO2007005381A3 PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT 审中-公开
公开(公告)号：WO2007005381A3
公开(公告)日：2007-01-11
申请号：PCT/US2006/024843
申请日：2006-06-27
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , HEPLER, Edward, L. , GAZDA, Robert, G. , REZNIK, Alexander
发明人： HEPLER, Edward, L. , GAZDA, Robert, G. , REZNIK, Alexander
IPC分类号： H04J11/00
摘要： A protocol engine (PE) (210) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory (220) and a second memory (221). The shared memory (220) is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory (220) based on the control word. For receive processing, the PE retrieves received data from the shared memory (220) and processes it while moving the data to the second memory (221).

5. 发明申请

WO2008008512A2 SYMBOL RATE HARDWARE ACCELERATOR 审中-公开
标题翻译：符号率硬件加速器
公开(公告)号：WO2008008512A2
公开(公告)日：2008-01-17
申请号：PCT/US2007/016031
申请日：2007-07-12
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , HEPLER, Edward, L.
发明人： HEPLER, Edward, L.
IPC分类号： H04L1/00
CPC分类号： H04L1/0043 , H04L1/0065 , H04L1/0071
摘要： A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.
摘要翻译：硬件加速器包括第一缓冲器，第二缓冲器，地址生成器，翻译只读存储器（ROM），循环冗余校验（CRC）生成器，卷积编码器和卷积编码器控制器。第一和第二缓冲器存储信息位。地址生成器生成用于访问第一缓冲器，第二缓冲器和共享存储器体系结构（SMA）的地址。翻译ROM用于生成用于访问第一缓冲区和第二缓冲区的翻译地址。控制器为CRC生成器，卷积编码器和地址生成器设置参数，并对信息执行用于信道处理（诸如重新排序，块编码，奇偶拖尾，穿孔，卷积编码和交织）的预定义序列的控制命令通过在第一缓冲器，第二缓冲器，SMA，CRC发生器和卷积编码器之间移动信息比特的同时操纵信息比特来实现。

6. 发明申请

WO2004080087A2 RECEIVED COMMUNICATION SIGNAL PROCESSING METHODS AND COMPONENTS FOR WIRELESS COMMUNICATION EQUIPMENT 审中-公开
标题翻译：接收通信信号处理方法及其无线通信设备的组件
公开(公告)号：WO2004080087A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/007049
申请日：2004-03-05
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , HEPLER, Edward, L. , FERRANTE, Steven , HACKETT, William, C. , REZNIK, Alexander , BOHNHOFF, Peter , MEYER, Jan
发明人： HEPLER, Edward, L. , FERRANTE, Steven , HACKETT, William, C. , REZNIK, Alexander , BOHNHOFF, Peter , MEYER, Jan
IPC分类号： H04Q
CPC分类号： H04B1/7113 , H04B1/70735 , H04B1/70755 , H04B1/708 , H04B1/7083 , H04B1/7117 , H04B7/08 , H04B17/364 , H04J13/10 , H04L25/0212
摘要： A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications. A selectively controllable coherent accumulation unit produces power delay profiles (PDPs). A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths.
摘要翻译：在无线通信系统中使用无线发射接收单元（WTRU）和方法来处理采样的接收信号以建立和/或维持无线通信。选择性可控相干累加单元产生功率延迟分布（PDP）。有选择地可控的后处理单元将阈值限幅值近似值和PDP位置传送到诸如瑞克接收机的设备以确定接收信号路径。

7. 发明申请

WO2007002202A2 METHOD AND APPARATUS FOR EFFICIENT OPERATION OF AN ENHANCED DEDICATED CHANNEL 审中-公开
标题翻译：用于有效操作增强专用信道的方法和设备
公开(公告)号：WO2007002202A2
公开(公告)日：2007-01-04
申请号：PCT/US2006/024154
申请日：2006-06-20
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , REZNIK, Alexander , HEPLER, Edward, L. , ZHANG, Guodong , SMITH, Harry, Seth , PAN, Jung-Lin , WANG, Peter, Shaomin , RACHA, Renuka , GAZDA, Robert , TERRY, Stephen, E.
发明人： REZNIK, Alexander , HEPLER, Edward, L. , ZHANG, Guodong , SMITH, Harry, Seth , PAN, Jung-Lin , WANG, Peter, Shaomin , RACHA, Renuka , GAZDA, Robert , TERRY, Stephen, E.
IPC分类号： H04Q7/00
CPC分类号： H04W72/0406 , H04L1/1812 , H04L1/1854 , H04L1/1887 , H04L1/1896
摘要： A method and apparatus for efficient operation of an enhanced dedicated channel (E-DCH) are disclosed. A physical layer processing includes computation of various control parameters followed by actual processing of the data to be transmitted. In accordance with the present invention, the computation of the control parameters is performed asynchronously from the associated data operation. A medium access control (MAC) layer provides information needed for computation of the control parameters to the physical layer as early as possible, while the data is being processed in parallel. The provided data includes a hybrid automatic repeat request (H-ARQ) profile, a transport block size, power offset, or the like. By sending this data to the physical layer before MAC-e processing is complete, the latency constraint can be significantly relaxed.
摘要翻译：公开了一种用于高效操作增强型专用信道（E-DCH）的方法和设备。物理层处理包括计算各种控制参数，然后对要传输的数据进行实际处理。根据本发明，控制参数的计算是与关联数据操作异步执行的。媒体访问控制（MAC）层尽可能早地为控制参数计算所需的信息，而数据正在并行处理。所提供的数据包括混合自动重复请求（H-ARQ）简档，传输块大小，功率偏移等。通过在MAC-e处理完成之前将此数据发送到物理层，可以显着放宽延迟限制。

8. 发明申请

WO2006020283A2 HIGH SPEED DOWNLINK PACKET ACCESS CO-PROCESSOR FOR UPGRADING THE CAPABILITIES OF AN EXISTING MODEM HOST 审中-公开
标题翻译：用于升级现有调制解调器主机能力的高速下行链路分组接入协同处理器
公开(公告)号：WO2006020283A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/025540
申请日：2005-07-19
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , HACKETT, William, C. , DIFAZIO, Robert, A. , HEPLER, Edward, L. , REZNIK, Alexander , CASTOR, Douglas, R. , ZEIRA, Ariela , GAZDA, Robert, G. , KAEWELL, John, David, Jr.
发明人： HACKETT, William, C. , DIFAZIO, Robert, A. , HEPLER, Edward, L. , REZNIK, Alexander , CASTOR, Douglas, R. , ZEIRA, Ariela , GAZDA, Robert, G. , KAEWELL, John, David, Jr.
IPC分类号： H04B7/216
CPC分类号： H04B1/707 , H04B1/406 , H04B2201/70707 , H04B2201/709727 , H04L2025/03509 , H04W88/02
摘要： A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.
摘要翻译：一种用于处理码分多址（CDMA）信号的无线发射/接收单元（WTRU）。 WTRU包括调制解调器主机和通过多个可定制接口进行通信的高速下行链路分组接入（HSDPA）协处理器。调制解调器主机根据第三代合作伙伴计划（3GPP）版本4（R4）标准进行操作，并且HSDPA协处理器整体上增强了WTRU的无线通信能力，使得WTRU根据3GPP版本5（ R5）标准。

9. 发明申请

WO2005117329A2 DATA-MOVER CONTROLLER WITH PLURAL REGISTERS FOR SUPPORTING CIPHERING OPERATIONS 审中-公开
标题翻译：数据移动控制器具有多个用于支持操作的寄存器
公开(公告)号：WO2005117329A2
公开(公告)日：2005-12-08
申请号：PCT/US2005/016026
申请日：2005-05-06
申请人： INTERDIGITAL TECHNOLOGY CORPORATION , HEPLER, Edward, L. , GAZDA, Robert, G.
发明人： HEPLER, Edward, L. , GAZDA, Robert, G.
IPC分类号： H04L9/00
CPC分类号： H04L63/0428 , G06F21/72 , G06F21/85 , H04W12/02
摘要： A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm "f8" or integrity cipher algorithm "f9".
摘要翻译：数据处理系统在第一存储器单元和第二存储器单元之间加密和传输数据，例如在共享存储器架构（SMA）静态随机存取存储器（SRAM）和双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）。该系统包括加密引擎和数据移动器控制器。数据移动器控制器包括至少一个具有指定所传输的数据是否应被加密的字段的寄存器。如果该字段指定传输的数据应该被加密，则该字段还指定要执行的加密类型，例如第三代合作伙伴计划（3GPP）标准化的机密密码算法“f8”或完整性密码算法“f9” 。

10. 发明申请

WO2009134846A1 METHOD AND APPARATUS FOR CONTENTION-FREE INTERLEAVING USING A SINGLE MEMORY 审中-公开
标题翻译：使用单个存储器进行无间断交换的方法和装置
公开(公告)号：WO2009134846A1
公开(公告)日：2009-11-05
申请号：PCT/US2009/042046
申请日：2009-04-29
申请人： INTERDIGITAL PATENT HOLDINGS, INC. , HEPLER, Edward, L. , NARAYAN, Geetha, L.
发明人： HEPLER, Edward, L. , NARAYAN, Geetha, L.
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2764 , H03M13/2957 , H04L1/0071
摘要： A method and apparatus for contention free interleaving are disclosed. A single memory configured to use an address scheme wherein the most significant bits (MSBs) indicate which word in memory stores an interleaved piece of data. The least significant bits (LSBs) are used to calculate an index that identifies a specific soft-in/soft-out (SISO) decoder associated with a sub-word of the retrieved data. Using an interleaved address generator, the extrinsic data may be written into the memory in sequential order, but read out from the memory in interleaved order, effectively de-interleaving the data so it may be decoded. The generated interleaved address is used by SISO selector circuit which controls a multiplexer that routes the sub-word to its appropriate SISO decoder. The same address generator may be used to write interleaved extrinsic data from SISOs by reordering the sub-words, allowing the extrinsic data to be read in sequential order.
摘要翻译：公开了一种无争用交错的方法和装置。配置为使用地址方案的单个存储器，其中最高有效位（MSB）指示存储器中的哪个字存储交错数据段。最低有效位（LSB）用于计算识别与检索的数据的子字相关联的特定软入/软出（SISO）解码器的索引。使用交错地址生成器，外部数据可以按顺序写入存储器，但是以交错顺序从存储器读出，有效地对数据进行解交织，以便其被解码。生成的交错地址由SISO选择器电路使用，SISO选择器电路控制将子字路由到其适当的SISO解码器的多路复用器。相同的地址生成器可以用于通过重新排序子字来从SISO写入交织的外部数据，从而允许按顺序读取外部数据。

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