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1. 发明申请

WO2006007350A1 HIGH MOBILITY TRI-GATE DEVICES AND METHODS OF FABRICATION 审中-公开
标题翻译：高移动三门设备和制造方法
公开(公告)号：WO2006007350A1
公开(公告)日：2006-01-19
申请号：PCT/US2005/020339
申请日：2005-06-08
申请人： INTEL CORPORATION , SHAHEEN, Mohamad, A. , DOYLE, Brian , DATTA, Suman , CHAU, Robert, S. , TOLCHINSKY, Peter
发明人： SHAHEEN, Mohamad, A. , DOYLE, Brian , DATTA, Suman , CHAU, Robert, S. , TOLCHINSKY, Peter
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L21/76243 , H01L21/76254 , H01L21/76256 , H01L29/045 , H01L29/66772
摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.
摘要翻译：高迁移率半导体组件。在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过约45度。

2. 发明申请

WO2006053331A1 METHOD FOR MANUFACTURING A SILICON-ON-INSULATOR (SOI) WAFER WITH AN ETCH STOP LAYER 审中-公开
标题翻译：具有阻塞层的硅绝缘体（SOI）波形的制造方法
公开(公告)号：WO2006053331A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/041544
申请日：2005-11-09
申请人： INTEL CORPORATION , TOLCHINSKY, Peter , GILES, Martin , MCSWINEY, Michael , SHAHEEN, Mohamad , YABLOK, Irwin
发明人： TOLCHINSKY, Peter , GILES, Martin , MCSWINEY, Michael , SHAHEEN, Mohamad , YABLOK, Irwin
IPC分类号： H01L21/762 , H01L21/265 , H01L21/316 , H01L21/318 , H01L21/78 , H01L21/82
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer (130) overlying the buried oxide layer (120) , as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
摘要翻译：公开了具有覆盖在掩埋氧化物层（120）上的蚀刻停止层（130）的绝缘体上硅（SOI）晶片的实施例，以及制造其的方法的实施例。蚀刻停止层可以包括氮化硅，氮掺杂二氧化硅或氮氧化硅，以及这些材料的某些组合。描述和要求保护其他实施例。

3. 发明申请

WO2014086742A1 EPITAXIAL WAFER AND A METHOD OF MANUFACTURING THEREOF 审中-公开
标题翻译：外延波形及其制造方法
公开(公告)号：WO2014086742A1
公开(公告)日：2014-06-12
申请号：PCT/EP2013/075313
申请日：2013-12-03
申请人： SILTRONIC AG , INTEL CORPORATION
发明人： STORCK, Peter , WERNER, Norbert , VORDERWESTNER, Martin , TOLCHINSKY, Peter , YABLOK, Irwin
IPC分类号： H01L21/20 , H01L21/223
CPC分类号： H01L21/3225 , H01L21/02381 , H01L21/02532 , H01L21/0254 , H01L21/0257 , H01L21/02573 , H01L21/0262 , H01L21/3221 , H01L29/167
摘要： Epitaxial wafer, comprising a silicon substrate wafer having a first side and a second side, and a silicon epitaxial layer deposited on the first side of the silicon substrate wafer, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, the silicon epitaxial layer being doped with nitrogen at a concentration of 1 x 10 16 atoms/cm 3 or more and 1 x 10 20 atoms/cm 3 or less, or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1 x 10 16 atoms/cm 3 or more and 1 x 10 20 atoms/cm 3 or less, or the silicon epitaxial layer and at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1 x 10 16 atoms/cm 3 or more and 1 x 10 20 atoms/cm 3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer or at least one of the one or more additional epitaxial layers, or the silicon epitaxial layer and at least one of the one or more additional epitaxial layers at a deposition temperature of 940°C or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.
摘要翻译：包括具有第一侧和第二侧的硅衬底晶片和沉积在硅衬底晶片的第一侧上的硅外延层以及可选地在硅外延层的顶部上的一个或多个附加外延层的外延晶片，硅外延层掺杂浓度为1×1016原子/厘米3以上且1×1020原子/厘米3以下的氮，或者所述一个或多个附加外延层中的至少一个掺杂浓度为1的氮 x 1016原子/ cm3以上且1×10 10原子/ cm 3以下，或者硅外延层，并且所述一个或多个另外的外延层中的至少一个掺杂有浓度为1×10 16原子/ cm 3以上的氮和1×1020原子/ cm3以下。通过在940℃的沉积温度下沉积硅外延层或一个或多个另外的外延层中的至少一个或者硅外延层和一个或多个另外的外延层中的至少一个来制造外延晶片，或在含有一种或多种硅前体化合物和一种或多种氮前体化合物的沉积气体气氛的存在下，通过化学气相沉积较少。

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