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1. 发明申请

WO2009017997A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ABRUPT ULTRA SHALLOW EPI-TIP REGIONS 审中-公开
标题翻译：形成具有超声波超低温区域的半导体器件的方法
公开(公告)号：WO2009017997A1
公开(公告)日：2009-02-05
申请号：PCT/US2008/070604
申请日：2008-07-21
申请人： INTEL CORPORATION , RACHMADY, Willy , KEATING, Steven , SELL, Bernhard
发明人： RACHMADY, Willy , KEATING, Steven , SELL, Bernhard
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.
摘要翻译：一种用于形成具有突变的超浅表面尖端区域的半导体器件的方法包括在晶体衬底上形成栅极堆叠，执行第一离子注入工艺以使位于邻近和相对侧两侧的衬底的第一对区域非晶化所述栅堆叠在所述衬底上形成一对间隔物，所述衬底设置在所述栅堆叠的横向相对侧上，执行第二离子注入工艺以使位于所述栅叠层的横向相对侧上的所述衬底的第二对区域非晶化;以及邻近所述间隔物，施加选择性湿法蚀刻化学物质以去除所述非晶化的第一和第二对区域并在所述栅极堆叠的横向相对侧上形成一对空腔，以及在所述一对空腔中沉积硅合金以形成源和漏极区域和源极和漏极表面尖端区域。

2. 发明申请

WO2013101109A1 SUB-SECOND ANNEALING LITHOGRAPHY TECHNIQUES 审中-公开
标题翻译：第二次退火光刻技术
公开(公告)号：WO2013101109A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067931
申请日：2011-12-29
申请人： INTEL CORPORATION , KILLAMPALLI, Aravind S. , WALLACE, Charles H. , SELL, Bernhard
发明人： KILLAMPALLI, Aravind S. , WALLACE, Charles H. , SELL, Bernhard
IPC分类号： H01L21/027
CPC分类号： H01L21/2636 , G03F7/40 , H01L21/0273 , H01L21/0337
摘要： Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.
摘要翻译：公开了用于将光刻特征的亚秒级退火的技术，例如，在一个，两个或三个维度上裁剪或以其他方式选择性地改变其轮廓。或者，或除此之外，可以使用技术来例如平滑或以其它方式减少光致抗蚀剂线宽度/边缘粗糙度和/或降低缺陷密度。在一些情况下，亚秒级退火工艺具有可以有效地改变一个或多个维度中的抗蚀剂收缩量的时间 - 温度分布，或以所需的方式（例如使光刻胶光滑）修饰抗蚀剂。这些技术可以例如使用任何类型的光致抗蚀剂（例如有机，无机，混合，分子光刻胶材料）来实现，并且可以用于形成例如处理器微架构，存储器电路，逻辑阵列和许多其它数字 /模拟/混合集成半导体器件。

3. 发明申请

WO2019125497A1 INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2019125497A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/068359
申请日：2017-12-22
申请人： INTEL CORPORATION , LAJOIE, Travis , GHANI, Tahir , KAVALIEROS, Jack T. , OGADHOH, Shem O. , WANG, Yih , SELL, Bernhard , GARDINER, Allen , LIN, Blake , ALZATE VINASCO, Juan G. , WANG, Pei-Hua , KU, Chieh-Jen , SHARMA, Abhishek A.
发明人： LAJOIE, Travis , GHANI, Tahir , KAVALIEROS, Jack T. , OGADHOH, Shem O. , WANG, Yih , SELL, Bernhard , GARDINER, Allen , LIN, Blake , ALZATE VINASCO, Juan G. , WANG, Pei-Hua , KU, Chieh-Jen , SHARMA, Abhishek A.
IPC分类号： H01L21/768
摘要： Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

4. 发明申请

WO2006074438A1 DEVICE WITH STEPPED SOURCE/DRAIN REGION PROFILE 审中-公开
标题翻译：具有步进源/排水区域配置的设备
公开(公告)号：WO2006074438A1
公开(公告)日：2006-07-13
申请号：PCT/US2006/000686
申请日：2006-01-05
申请人： INTEL CORPORATION , CURELLO, Guiseppe , SELL, Bernhard , TYAGI, Sunit , AUTH, Chris
发明人： CURELLO, Guiseppe , SELL, Bernhard , TYAGI, Sunit , AUTH, Chris
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7842
摘要： Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.
摘要翻译：本发明的实施例提供具有阶梯式源极和漏极区域的晶体管。台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯形凹陷，并且在凹部中形成源极/漏极区域。

5. 发明申请

WO2006039641A3 IMPROVING SHORT CHANNEL EFFECT OF MOS DEVICES BY RETROGRADE WELL ENGINEERING USING TILTED DOPANT IMPLANTATION INTO RECESSED SOURCE/DRAIN REGIONS 审中-公开
公开(公告)号：WO2006039641A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/035474
申请日：2005-09-29
申请人： INTEL CORPORATION , HOFFMANN, Thomas , TYAGI, Sunit , CURELLO, Giuseppe , SELL, Bernhard , AUTH, Christopher
发明人： HOFFMANN, Thomas , TYAGI, Sunit , CURELLO, Giuseppe , SELL, Bernhard , AUTH, Christopher
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
摘要： A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

6. 发明申请

WO2013095550A1 SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH 审中-公开
标题翻译：具有半导体器件的半导体器件和形成变化宽度的半导体器件的方法
公开(公告)号：WO2013095550A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066991
申请日：2011-12-22
申请人： INTEL CORPORATION , SELL, Bernhard
发明人： SELL, Bernhard
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/02532 , H01L21/30604 , H01L21/3083 , H01L21/823412 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/16 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/6681 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
摘要翻译：描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。例如，半导体器件包括设置在衬底上方的半导体本体。栅电极堆叠设置在半导体本体的一部分上，以在栅极电极堆叠下方限定半导体本体中的沟道区。源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

7. 发明申请

WO2010002718A3 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY 审中-公开
公开(公告)号：WO2010002718A3
公开(公告)日：2010-01-07
申请号：PCT/US2009/048764
申请日：2009-06-26
申请人： INTEL CORPORATION , SELL, Bernhard , GOLONZKA, Oleg
发明人： SELL, Bernhard , GOLONZKA, Oleg
IPC分类号： H01L21/28
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.

8. 发明申请

WO2008121659A1 SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED EPITAXIAL SOURCE AND DRAIN EXTENSIONS 审中-公开
标题翻译：具有自对准外延源和漏极延伸的半导体器件
公开(公告)号：WO2008121659A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/058325
申请日：2008-03-26
申请人： INTEL CORPORATION , SELL, Bernhard , GHANI, Tahir , MURTHY, Anand , GOMEZ, Harry
发明人： SELL, Bernhard , GHANI, Tahir , MURTHY, Anand , GOMEZ, Harry
IPC分类号： H01L21/20
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
摘要翻译：一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底的区域中，其中掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料基质。

9. 发明申请

WO2007112228A1 STRUCTURE AND FABRICATION METHOD OF A SELECTIVELY DEPOSITED CAPPING LAYER ON AN EPITAXIALLY GROWN SOURCE DRAIN 审中-公开
标题翻译：一种选择性沉积的覆盖层的结构和制造方法
公开(公告)号：WO2007112228A1
公开(公告)日：2007-10-04
申请号：PCT/US2007/064295
申请日：2007-03-19
申请人： INTEL CORPORATION , COOK, Ted, Jr. , SELL, Bernhard , MURTHY, Anand
发明人： COOK, Ted, Jr. , SELL, Bernhard , MURTHY, Anand
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is doped in situ with Boron in the source region and in the drain region. Silicon is deposited on the Silicon Germanium alloy. Nickel is deposited on the Silicon. A Nickel Silicon Germanium silicide layer is formed on the Silicon Germanium alloy. A Nickel Silicon silicide layer is formed on the Nickel Silicon Germanium silicide layer.
摘要翻译：公开了一种改善硅化物的接触形成并降低晶体管的外部电阻的方法和装置。在基板的表面上形成栅电极。源极区域和漏极区域在基板中各向同性地蚀刻。在源区和漏区中硼原位掺杂硅锗合金。硅沉积在硅锗合金上。镍沉积在硅上。在硅锗合金上形成硅锗硅化硅层。镍硅化硅层形成在硅锗硅化硅层上。

10. 发明申请

WO2005117130A3 STEPPED TIP JUNCTION WITH SPACER LAYER 审中-公开
公开(公告)号：WO2005117130A3
公开(公告)日：2005-12-08
申请号：PCT/US2005/014969
申请日：2005-04-29
申请人： INTEL CORPORATION , BAN, Ibrahim , SELL, Bernhard , NATARAJAN, Sanjay , BOHR, Mark
发明人： BAN, Ibrahim , SELL, Bernhard , NATARAJAN, Sanjay , BOHR, Mark
IPC分类号： H01L29/78 , H01L21/336
摘要： Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer lacer.

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