专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013147898A1 TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS 审中-公开
标题翻译：用于记录多核处理器上共享存储器间隔的跟踪机制
公开(公告)号：WO2013147898A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031735
申请日：2012-03-30
申请人： INTEL CORPORATION , POKAM, Gilles A. , PEREIRA, Cristiano L. , ADL-TABATABA, Ali-reza
发明人： POKAM, Gilles A. , PEREIRA, Cristiano L. , ADL-TABATABA, Ali-reza
IPC分类号： G06F9/06 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F12/0815 , G06F9/30043 , G06F11/3636 , G06F12/023 , G06F13/1663 , G06F2212/622 , G11C7/1072 , Y02D10/14
摘要： A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.
摘要翻译：提供了一个记忆体记录器（MRR）。 MRR包括具有放松的存储器一致性模型的多核处理器，多核处理器的扩展，存储块的扩展，具有块大小（CS）和指令计数（IC）的块，以及多个的核心来执行指令。多个核向存储缓冲器（STB）和模拟存储器执行加载/存储指令，以在该值不在STB中时存储该值。当IC等于零并且CS大于零时，STB中的最旧值被传送到模拟存储器。 MRR记录包含CS，IC和全局时间戳的跟踪条目，全局时间戳记证明所有记录的块的总顺序。

2. 发明申请

WO2014052637A1 METHODS AND SYSTEMS FOR PERFORMING A REPLAY EXECUTION 审中-公开
标题翻译：执行重复执行的方法和系统
公开(公告)号：WO2014052637A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/061990
申请日：2013-09-26
申请人： INTEL CORPORATION , GOTTSCHLICH, Justin E. , DANNE, Klaus , PEREIRA, Cristiano L. , POKAM, Gilles A. , KASSA, Rolf , HU, Shiliang , KRANICH, Tim
发明人： GOTTSCHLICH, Justin E. , DANNE, Klaus , PEREIRA, Cristiano L. , POKAM, Gilles A. , KASSA, Rolf , HU, Shiliang , KRANICH, Tim
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3005 , G06F9/30072 , G06F9/3802 , G06F9/3851 , G06F9/44 , G06F9/455 , G06F9/52 , G06F11/30 , G06F11/3414 , G06F11/3476 , G06F11/36 , G06F11/3664 , G06F11/3688 , G06F2201/815 , G06F2201/825 , G06F2201/865
摘要： One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.
摘要翻译：一个或多个实施例可以提供用于执行重放的方法。该方法包括启动程序的执行，程序具有多组指令，并且每组指令具有多个指令块。该方法还包括通过在处理器上执行的虚拟机单元截取在执行之前块数量的指令。该方法还包括通过在处理器上执行的重播模块确定该块是否是活动块，并且响应于该块作为活动块来执行该指令。

3. 发明申请

WO2014143059A1 MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS 审中-公开
标题翻译：促进计算机系统软件程序中指导性原子动力的动态和有效管理的机制
公开(公告)号：WO2014143059A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/032640
申请日：2013-03-15
申请人： INTEL CORPORATION , DAUTENHAHN, Nathan , GOTTSCHLICH, Justin E. , POKAM, Gilles A. , PEREIRA, Cristiano L. , HU, Shiliang , DANNE, Klaus , KASSA, Rolf
发明人： DAUTENHAHN, Nathan , GOTTSCHLICH, Justin E. , POKAM, Gilles A. , PEREIRA, Cristiano L. , HU, Shiliang , DANNE, Klaus , KASSA, Rolf
IPC分类号： G06F11/28 , G06F11/36 , G06F9/46
CPC分类号： G06F9/30145 , G06F9/3009 , G06F9/3895 , G06F9/3897 , G06F9/52 , G06F11/0724 , G06F11/1438 , G06F11/1484 , G06F11/3636
摘要： A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.
摘要翻译：描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。记录系统可以记录第一和第二宏指令之间的交织。该方法包括在发生时准确地重播第一和第二宏指令的交错记录。正确重放可以包括重放第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

4. 发明申请

WO2012087402A1 METHOD AND SYSTEM FOR DETECTING ABNORMAL INTERLEAVINGS IN CONCURRENT PROGRAMS 审中-公开
标题翻译：用于检测同步程序中异常交互的方法和系统
公开(公告)号：WO2012087402A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/054081
申请日：2011-09-29
申请人： INTEL CORPORATION , JALBERT, Nicholas A. , PEREIRA, Cristiano L. , POKAM, Gilles A.
发明人： JALBERT, Nicholas A. , PEREIRA, Cristiano L. , POKAM, Gilles A.
IPC分类号： G06F11/28 , G06F11/36 , G06F9/38 , G06F9/06
CPC分类号： G06F11/1479 , G06F9/3851 , G06F11/3632
摘要： A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.
摘要翻译：一种用于检测多线程程序中的异常交织的方法和系统，包括响应于多线程程序的执行而生成执行日志。基于执行日志，如果多线程程序的执行导致没有并发错误，并且如果多线程程序的执行导致一个或多个程序执行，则生成可疑立即交织列表，则生成允许的立即交织的列表更多的并发错误。将第一和第二列表进行比较以产生造成误差的立即交错的列表。然后基于造成错误的即时交错的列表来生成并执行可重放的核心。

5. 发明申请

WO2015088534A1 TECHNIQUES FOR DETECTING RACE CONDITIONS 审中-公开
标题翻译：检测条件的技术
公开(公告)号：WO2015088534A1
公开(公告)日：2015-06-18
申请号：PCT/US2013/074661
申请日：2013-12-12
申请人： INTEL CORPORATION , HU, Shiliang , POKAM, Gilles A. , PEREIRA, Cristiano L. , GOTTSCHLICH, Justin E.
发明人： HU, Shiliang , POKAM, Gilles A. , PEREIRA, Cristiano L. , GOTTSCHLICH, Justin E.
IPC分类号： G06F11/36 , G06F11/28
CPC分类号： G06F11/3632 , G06F9/526 , G06F11/0715 , G06F11/0778 , G06F11/30 , G06F11/3409 , G06F11/3419 , G06F11/3466 , G06F11/366
摘要： Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及通过检测与这种访问相关联的所选择的高速缓存事件的发生来检测由应用程序的不同部分的未协调数据访问引起的竞争条件。一种装置包括处理器组件; 触发组件，用于由处理器组件执行以配置处理器组件的监控单元以检测与对一条数据的访问之间的竞争条件相关联的高速缓存事件，并且捕获处理器组件的状态的指示以生成监视响应于缓存事件的发生的数据; 以及用于由处理器组件执行以配置监视单元的计数器的计数器组件，以使得能够以小于高速缓存事件的每次出现的频率捕获处理器组件的状态的指示。描述和要求保护其他实施例。

6. 发明申请

WO2014142820A1 VISUALIZING RECORDED EXECUTIONS OF MULTI-THREADED SOFTWARE PROGRAMS FOR PERFORMANCE AND CORRECTNESS 审中-公开
标题翻译：可视化多线程软件程序的性能和正确性的记录执行
公开(公告)号：WO2014142820A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/030745
申请日：2013-03-13
申请人： INTEL CORPORATION , GOTTSCHLICH, Justin E. , POKAM, Gilles A. , PEREIRA, Cristiano L. , DANNE, Klaus , SHILIANG, Hu , KASSA, Rolf
发明人： GOTTSCHLICH, Justin E. , POKAM, Gilles A. , PEREIRA, Cristiano L. , DANNE, Klaus , SHILIANG, Hu , KASSA, Rolf
IPC分类号： G06F9/46 , G06T1/00
CPC分类号： G06F11/3664 , G06F9/38 , G06F11/323 , G06F11/3404 , G06F2201/865 , G06T11/206 , G06T13/80
摘要： A system graphically visualizes performance and/or correctness features of a recorded execution of a multi-threaded software program. The system may process chunk-based information recorded during an execution of the multi-threaded program, prepare a graphical visualization of the recorded information, and display the graphical visualization on a display in an animated fashion. The system may allow a viewer to interactively control the display of the animated graphical visualization.
摘要翻译：系统以图形方式可视化多线程软件程序的记录执行的性能和/或正确性特征。系统可以处理在执行多线程程序期间记录的基于块的信息，准备所记录信息的图形可视化，并以动画方式在显示器上显示图形可视化。系统可以允许观看者交互地控制动画图形可视化的显示。

7. 发明申请

WO2015148608A1 ENABLING MAXIMUM CONCURRENCY IN A HYBRID TRANSACTIONAL MEMORY SYSTEM 审中-公开
标题翻译：在混合的交易记忆系统中实现最大的一致性
公开(公告)号：WO2015148608A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022394
申请日：2015-03-25
申请人： INTEL CORPORATION
发明人： CALCIU, Irina , GOTTSCHLICH, Justin E. , SHPEISMAN, Tatiana , POKAM, Gilles A.
IPC分类号： G06F9/38 , G06F17/30
CPC分类号： G06F9/467 , G06F9/528
摘要： In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.
摘要翻译：在事务性存储器系统的实施例中，一种装置包括处理器和执行逻辑，以使得能够并行执行第一软件交易模式和第二软件交易模式的第二软件交易的至少一个第一软件交易，并且至少一个第一硬件事务模式的硬件事务和第二硬件事务模式的至少一个第二硬件事务。在一个示例中，执行逻辑可以在处理器内实现。描述和要求保护其他实施例。

8. 发明申请

WO2016160192A1 TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS 审中-公开
标题翻译：技术因素导致无使用内存损坏BUG的识别
公开(公告)号：WO2016160192A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/019586
申请日：2016-02-25
申请人： INTEL CORPORATION
发明人： GOTTSCHLICH, Justin E. , POKAM, Gilles A. , PEREIRA, Cristiano L.
IPC分类号： G06F11/36 , G06F11/16
CPC分类号： G06F11/079 , G06F11/073
摘要： Technologies for identification of a potential root cause of a use-after-free memory corruption bug of a program include a computing device to replay execution of the execution of the program based on an execution log of the program. The execution log comprises an ordered set of executed instructions of the program that resulted in the use-after-free memory corruption bug. The computing device compares a use-after-free memory address access of the program to a memory address associated with an occurrence of the use-after-free memory corruption bug in response to detecting the use-after-free memory address access and records the use-after-free memory address access of the program as a candidate for a root cause of the use-after-free memory corruption bug to a candidate list in response to detecting a match between the use-after-free memory address access of the program and the memory address associated with the occurrence of the use-after-free memory corruption bug.
摘要翻译：用于识别程序的无使用存储器内存损坏错误的潜在根本原因的技术包括基于程序的执行日志来重放执行程序的计算设备。执行日志包括导致使用随机存储器内存损坏错误的程序的有序执行指令集。所述计算装置响应于检测到所述无用存储器存储器地址访问来比较所述程序的使用随机存储器地址访问与与所述无使用存储器内存损坏错误的发生相关联的存储器地址，并记录响应于检测到所述无用存储器内存地址访问之间的匹配，将所述程序的无用空闲内存地址访问作为候选列表的候选者，作为所述无用存储器内存损坏错误的根本原因程序和与使用随机存储器内存损坏错误的发生相关联的存储器地址。

9. 发明申请

WO2017172128A1 INSTRUCTION, CIRCUITS, AND LOGIC FOR DATA CAPTURE FOR SOFTWARE MONITORING AND DEBUGGING 审中-公开
标题翻译：用于软件监视和调试的指令，电路和数据捕获逻辑
公开(公告)号：WO2017172128A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019063
申请日：2017-02-23
申请人： INTEL CORPORATION
发明人： PEREIRA, Cristiano L. , POKAM, Gilles A. , HU, Shiliang , STRONG, Beeman C.
IPC分类号： G06F11/34 , G06F12/02
CPC分类号： G06F12/0875 , G06F11/3034 , G06F11/3466 , G06F12/0842 , G06F12/0888 , G06F2201/865 , G06F2212/452
摘要： A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.
摘要翻译：处理器包括：前端，其包括用于接收监视线程的执行的指令的电路，包括用于对指令进行解码的电路的解码器，包括用于调度指令的电路的调度器，包括电路的退役单元退休指令，和一个核心。内核包括用于基于指令的执行来监视线程的执行，在线程的执行期间识别对地址的尝试读取，确定在监视线程的执行期间先前是否读取了地址处的值的电路，基于确定在监视线程的执行期间以前未读取地址处的值来确定尝试的读取，并且基于在监视期间之前读取的地址处的值的确定而省略尝试的读取的记录线程的执行情况。

10. 发明申请

WO2015148339A1 SOFTWARE REPLAYER FOR TRANSACTIONAL MEMORY PROGRAMS 审中-公开
标题翻译：用于实时存储器程序的软件更新程序
公开(公告)号：WO2015148339A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/021929
申请日：2015-03-23
申请人： INTEL CORPORATION
发明人： GOTTSCHLICH, Justin E. , POKAM, Gilles A. , HU, Shiliang , KASSA, Rolf , WU, Youfeng , CALCIU, Irina
IPC分类号： G06F9/455 , G06F11/36
CPC分类号： G06F9/467 , G06F11/34 , G06F11/362 , G06F11/3648
摘要： A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.
摘要翻译：公开了一种包括处理器和动态随机存取存储器（DRAM）的系统。处理器包括包括硬件事务存储器（HTM）的混合事务处理存储器（HyTM），并且使用HyTM执行用于重放包括HTM指令并已被执行的程序的程序调试器。程序调试器包括一个软件仿真器，通过仿真HTM来重播HTM指令。公开和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式