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1. 发明申请

WO2019132942A1 INTEGRATION OF ACTIVE AND PASSIVE COMPONENTS WITH III-V TECHNOLOGY 审中-公开
公开(公告)号：WO2019132942A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068816
申请日：2017-12-28
申请人： INTEL CORPORATION , LIN, Kevin L. , FISCHER, Paul B. , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
发明人： LIN, Kevin L. , FISCHER, Paul B. , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
IPC分类号： H01L29/778 , H01L29/66 , H01L21/768
摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device that may include a transistor and a passive element. The semiconductor device may include a substrate. A layer of III-V material may be above the substrate, the layer of III-V material including at least GaN. The layer of III-V material may include a first area, and a second area separated from the first area by an isolation area. The transistor may be above the first area in the layer of III-V material, and the passive element may be above the second area in the layer of III-V material. In addition, a resonator including a first electrode and a second electrode may be formed within a shadow of a third area separated from the first area by an isolation area. Other embodiments may be described and/or claimed.

2. 发明申请

WO2014105147A1 METHOD, APPARATUS AND SYSTEM FOR PROVIDING METERING OF ACCELERATION 审中-公开
标题翻译：方法，提供加速度计的装置和系统
公开(公告)号：WO2014105147A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046822
申请日：2013-06-20
申请人： INTEL CORPORATION , LIN, Kevin L. , EID, Faras , MA, Qing
发明人： LIN, Kevin L. , EID, Faras , MA, Qing
IPC分类号： G01P15/105 , G01C19/56 , B81B3/00
CPC分类号： G01P15/105 , G01P15/08
摘要： Techniques and mechanisms to provide for metering acceleration. In an embodiment, a microelectromechanical accelerometer includes a magnet, a mass, and a first support beam portion and second support beam portion for suspension of the mass. Resonance frequency characteristics of the first support beam portion and second support beam portion, based on the magnet and a current conducted by the first support beam portion and second support beam portion, are indicative of acceleration of the mass. In another embodiment, the accelerometer further includes a first wire portion and a second wire portion which are each coupled to the mass and further coupled to a respective anchor for exchanging a signal with the first wire portion and the second wire portion. The first wire portion and the second wire portion provide for biasing of the mass.
摘要翻译：提供计量加速度的技术和机制。在一个实施例中，微机电加速度计包括用于悬挂质量的磁体，质量块和第一支撑梁部分和第二支撑梁部分。基于磁体的第一支撑梁部分和第二支撑梁部分的共振频率特性以及由第一支撑梁部分和第二支撑梁部分传导的电流表示质量的加速度。在另一个实施例中，加速度计还包括第一线部分和第二线部分，每个第一线部分和第二线部分均耦合到质量块，并且还耦合到相应的锚，用于与第一线部分和第二线部分交换信号。第一线部分和第二线部分提供质量的偏压。

3. 发明申请

WO2018118092A1 ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES 审中-公开
公开(公告)号：WO2018118092A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068586
申请日：2016-12-23
申请人： INTEL CORPORATION , SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
发明人： SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
IPC分类号： H01L21/768 , H01L21/027
摘要： Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

4. 发明申请

WO2018118089A1 DIFFERENTIATED MOLECULAR DOMAINS FOR SELECTIVE HARDMASK FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018118089A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068582
申请日：2016-12-23
申请人： INTEL CORPORATION , HAN, Eungnak , HOURANI, Rami , GSTREIN, Florian , SINGH, Gurpreet , CLENDENNING, Scott B. , LIN, Kevin L. , CHANDHOK, Manish
发明人： HAN, Eungnak , HOURANI, Rami , GSTREIN, Florian , SINGH, Gurpreet , CLENDENNING, Scott B. , LIN, Kevin L. , CHANDHOK, Manish
IPC分类号： H01L21/768 , H01L21/033
摘要： Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

5. 发明申请

WO2018101961A1 SURFACE-ALIGNED LITHOGRAPHIC PATTERNING APPROACHES FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION 审中-公开
公开(公告)号：WO2018101961A1
公开(公告)日：2018-06-07
申请号：PCT/US2016/064684
申请日：2016-12-02
申请人： INTEL CORPORATION , BRISTOL, Robert L. , LIN, Kevin L. , BLACKWELL, James M.
发明人： BRISTOL, Robert L. , LIN, Kevin L. , BLACKWELL, James M.
IPC分类号： H01L21/768 , H01L21/027
摘要： Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above the plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

6. 发明申请

WO2018231195A1 AIR GAP STRUCTURES IN INTEGRATED CIRCUIT COMPONENTS 审中-公开
公开(公告)号：WO2018231195A1
公开(公告)日：2018-12-20
申请号：PCT/US2017/037122
申请日：2017-06-13
申请人： INTEL CORPORATION
发明人： LIN, Kevin L. , CHANDHOK, Manish
IPC分类号： H01L23/482 , H01L23/48 , H01L23/13 , H01L25/07
摘要： Disclosed herein are air gap structures in integrated circuit (IC) components. In some embodiments, an IC component may include: a first interconnect layer including an interconnect; a second interconnect layer including a conductive line and a conductive via, wherein the conductive via is in conductive contact with the interconnect; a sleeve of dielectric material at least partially laterally surrounding the conductive via; an anchor between the conductive line and the first interconnect layer, wherein the anchor includes a dielectric material; and an air gap around the sleeve and the anchor.

7. 发明申请

WO2018125111A1 SELF-ALIGNED VIA 审中-公开
公开(公告)号：WO2018125111A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069086
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： BLACKWELL, James M. , LIN, Kevin L. , BRISTOL, Robert L. , HOURANI, Rami
IPC分类号： H01L21/768
摘要： There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.

8. 发明申请

WO2017171760A1 SELF-ALIGNED VIA BELOW SUBTRACTIVELY PATTERNED INTERCONNECT 审中-公开
标题翻译：通过低于次要的相互连接自我对齐
公开(公告)号：WO2017171760A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025074
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： CHANDHOK, Manish , SCHENKER, Richard E. , YOO, Hui Jae , LIN, Kevin L. , CHAWLA, Jasmeet S. , BOJARSKI, Stephanie A. , SURI, Satyarth , CARVER, Colin T. , NASKAR, Sudipto
IPC分类号： H01L21/768 , H01L21/027
摘要： A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
摘要翻译：在衬底上的第一绝缘层上的互连层中形成多个互连部件。第一绝缘层中的开口穿过至少一个互连部件形成。空隙填充层沉积在开口中。

9. 发明申请

WO2018111289A1 INTERCONNECTS PROVIDED BY SUBTRACTIVE METAL SPACER BASED DEPOSITION 审中-公开
公开(公告)号：WO2018111289A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/067069
申请日：2016-12-16
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian
IPC分类号： H01L21/768 , H01L21/02 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/76885 , H01L23/5283
摘要： Disclosed herein are methods for manufacturing a metallization stack including a plurality of electrically conductive interconnects by subtractive metal spacer based deposition, and related semiconductor devices. For example, in some embodiments, a method of forming a semiconductor device may include providing a pattern of sacrificial elements over an interconnect support layer, depositing an electrically conductive material on sidewalls of the sacrificial elements, and removing the sacrificial elements so that the remaining portions of the electrically conductive material form a pattern of electrically conductive elements which can serve as interconnects of a metallization stack of the semiconductor device.

10. 发明申请

WO2018063322A1 SPACER-BASED PATTERNING FOR TIGHT-PITCH AND LOW-VARIABILITY RANDOM ACCESS MEMORY (RAM) BIT CELLS AND THE RESULTING STRUCTURES 审中-公开
标题翻译：用于间距和低变量随机访问存储器（RAM）位单元的细胞间距图形和结果结构
公开(公告)号：WO2018063322A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054760
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin L. , ATANASOV, Sarah E. , O'BRIEN, Kevin P. , BRISTOL, Robert L.
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/00 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/141 , H01L45/147 , H01L45/1675
摘要： Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.
摘要翻译：描述了用于窄间距和低变异性随机存取存储器（RAM）位单元的基于间隔的图案化以及所产生的结构。在一个示例中，半导体结构包括具有顶层的衬底。非易失性随机存取存储器（RAM）位单元的阵列设置在衬底的顶层上。非易失性RAM位单元阵列包括沿着第一方向的非易失性RAM位单元的列和沿着与第一方向正交的第二方向的非易失性RAM位单元的行。沿着非易失性RAM位单元阵列的列之间的第一方向，衬底的顶层中有多个凹槽。

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