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1. 发明申请

WO2014031207A1 A NETWORK CONTROLLER FOR REMOTE SYSTEM MANAGEMENT 审中-公开
标题翻译：一种用于远程系统管理的网络控制器
公开(公告)号：WO2014031207A1
公开(公告)日：2014-02-27
申请号：PCT/US2013/043312
申请日：2013-05-30
申请人： INTEL CORPORATION , GASPARAKIS, Iosif , GANGA, Ilango S. , WASKIEWICZ, Peter P. Jr.
发明人： GASPARAKIS, Iosif , GANGA, Ilango S. , WASKIEWICZ, Peter P. Jr.
IPC分类号： H04L12/24
CPC分类号： H04L29/0818 , H04L41/0816 , H04L43/0829 , H04L43/0888
摘要： Generally, this disclosure describes a network controller for remote system management. A host device may include the network controller and a programmable network element. The network controller may include controller circuitry configured to acquire network management data related to operation of the network controller and to receive host management data related to operation of the host device. The network controller may further include a transmitter configured to transmit the network and host management data to a management system remote from the network controller and a receiver configured to receive a command from the management system related to the management data, the command configured to reprogram the programmable network element to change a behavior of the programmable network element.
摘要翻译：通常，本公开描述了用于远程系统管理的网络控制器。主机设备可以包括网络控制器和可编程网元。网络控制器可以包括被配置为获取与网络控制器的操作相关的网络管理数据并且接收与主机设备的操作相关的主机管理数据的控制器电路。网络控制器还可以包括发射机，被配置为将网络和主机管理数据发送到远离网络控制器的管理系统，以及被配置为从管理系统接收与管理数据相关的命令的接收机，该命令被配置为重新编程可编程网元改变可编程网元的行为。

2. 发明申请

WO2013165410A1 PACKET PROCESSING OF DATA USING MULTIPLE MEDIA ACCESS CONTROLLERS 审中-公开
标题翻译：使用多媒体访问控制器的数据分组处理
公开(公告)号：WO2013165410A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/036108
申请日：2012-05-02
申请人： INTEL CORPORATION , GASPARAKIS, Iosif , WASKIEWICZ JR, Peter P. , GANGA, Ilango S. , HULETT, Terry V. , SARANGAM, Parthasarathy
发明人： GASPARAKIS, Iosif , WASKIEWICZ JR, Peter P. , GANGA, Ilango S. , HULETT, Terry V. , SARANGAM, Parthasarathy
IPC分类号： H04L12/56 , H04L29/12 , H04L29/10
CPC分类号： H04L67/02 , G06F9/45533 , H04L69/321
摘要： Examples are disclosed for a device having at least two media access controllers. In some examples, a first media access controller may be coupled to a host computing device. A second media access controller may be coupled to one or more processor circuits arranged to perform packet processing of data payloads for one or more data frames forwarded through the first media access controller and/or forwarded through the second media access controller. The first media access controller may be coupled to the second media access controller via a communication link. Other examples are described and claimed.
摘要翻译：公开了具有至少两个媒体访问控制器的设备的示例。在一些示例中，第一媒体访问控制器可以耦合到主计算设备。第二媒体接入控制器可以耦合到一个或多个处理器电路，其被布置为对通过第一媒体接入控制器转发的一个或多个数据帧执行数据有效载荷的分组处理和/或通过第二媒体接入控制器转发。第一媒体接入控制器可以经由通信链路耦合到第二媒体接入控制器。其他的例子被描述和要求保护。

3. 发明申请

WO2013081620A1 SERVER INCLUDING SWITCH CIRCUITRY 审中-公开
标题翻译：服务器包括开关电路
公开(公告)号：WO2013081620A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062912
申请日：2011-12-01
申请人： INTEL CORPORATION , VASUDEVAN, Anil , SARANGAM, Parthasarathy , GANGA, Ilango S.
发明人： VASUDEVAN, Anil , SARANGAM, Parthasarathy , GANGA, Ilango S.
IPC分类号： G06F13/14 , G06F15/16 , H04L29/02
CPC分类号： H04L41/04 , G06F13/385
摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.
摘要翻译：一个实施例可以包括至少一个可以至少部分地控制服务器交换机电路数据和控制平面处理的服务器处理器。所述至少一个处理器可以包括至少一个高速缓存存储器，其能够涉及涉及服务器的至少一个组件的至少一个数据传输。所述至少一个数据传送可以以服务器系统存储器的旁路方式进行。开关电路可以经由通信链路通信地耦合到至少一个处理器和至少一个节点。至少一个处理器可以至少部分地选择要由链路使用的至少一个通信协议。至少部分地，交换机电路经由至少一个链路至少一个接收的分组转发。许多修改是可能的。

4. 发明申请

WO2009042397A1 METHOD AND SYSTEM FOR VIRTUAL PORT COMMUNICATIONS 审中-公开
标题翻译：虚拟港口通信的方法和系统
公开(公告)号：WO2009042397A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/075773
申请日：2008-09-10
申请人： INTEL CORPORATION , GANGA, Ilango S.
发明人： GANGA, Ilango S.
IPC分类号： H04L12/54 , G06F15/16 , G06F9/46
CPC分类号： H04L45/745 , G06F9/45558 , G06F15/16 , G06F2009/45591 , G06F2009/45595 , H04L45/66
摘要： A method and system may provide virtual port communications. A data frame, containing a destination identifier in a destination field and payload, may be modified by inserting a first virtual machine tag therein. The first virtual machine tag may include a first virtual port identifier for identifying a first logical interface of a first virtual machine on a virtual machine host.
摘要翻译：方法和系统可以提供虚拟端口通信。可以通过在其中插入第一虚拟机标签来修改在目的地字段和有效载荷中包含目的地标识符的数据帧。第一虚拟机标签可以包括用于识别虚拟机主机上的第一虚拟机的第一逻辑接口的第一虚拟端口标识符。

5. 发明申请

WO2021225637A1 NETWORK AND EDGE ACCELERATION TILE (NEXT) ARCHITECTURE 审中-公开
公开(公告)号：WO2021225637A1
公开(公告)日：2021-11-11
申请号：PCT/US2020/067073
申请日：2020-12-26
申请人： INTEL CORPORATION
发明人： KUTCH, Patrick G. , CHILIKIN, Andrey , MCDONNELL, Niall D. , KEATING, Brian A. , LAKKAKULA, Naveen , GANGA, Ilango S. , KRISHNA IYER, Venkidesh , FLEMING, Patrick , MOSUR, Lokpraveen
IPC分类号： H04L12/935 , H04L12/879 , H04L12/861 , H04L12/867 , H04L12/937 , H04L12/851 , H04L29/08 , G06F9/50 , H04L29/06
摘要： Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

6. 发明申请

WO2017112143A1 METHODS AND APPARATUS FOR MULTI-STAGE VM VIRTUAL NETWORK FUNCTION AND VIRTUAL SERVICE FUNCTION CHAIN ACCELERATION FOR NFV AND NEEDS-BASED HARDWARE ACCELERATION 审中-公开
标题翻译：用于NFV和基于需求的硬件加速的多级虚拟机虚拟网络功能和虚拟服务功能链加速的方法和装置
公开(公告)号：WO2017112143A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062209
申请日：2016-11-16
申请人： INTEL CORPORATION
发明人： PALERMO, Stephen T. , WILLIS, Thomas E. , SOOD, Kapil , GANGA, Ilango S. , DUBAL, Scott P. , GANESH, Pradeepsunder , BRANDENBURG, Jesse C.
IPC分类号： H04L12/931 , G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45595 , H04L49/70
摘要： Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.
摘要翻译：用于NFV和基于需求的硬件加速的用于多阶段VM虚拟网络功能和虚拟服务功能链加速的方法和装置运行虚拟化环境的计算平台，包括运行执行网络功能虚拟化（NFV）的服务应用程序的虚拟机（VM），采用现场可编程门阵列（FPGA）为执行虚拟机到虚拟机和NFV到NFV提供基于硬件的快速路径传输。 FPGA以及相关的配置数据也被配置为支持硬件加速的动态分配和性能，以将处理任务从诸如云数据中心之类的虚拟化环境中的处理器卸载。

7. 发明申请

WO2016149212A1 ETHERNET AUTO-NEGOTIATION TECHNIQUES FOR DETERMINING LINK WIDTH 审中-公开
标题翻译：以太网自动调节技术用于确定链路宽度
公开(公告)号：WO2016149212A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/022365
申请日：2016-03-14
申请人： INTEL CORPORATION
发明人： RAN, Adee O. , GANGA, Ilango S. , LUSTED, Kent C.
IPC分类号： H04L12/935 , H04L12/931 , H04L12/805
CPC分类号： H04L12/413 , G06F13/4278 , H04L12/40182
摘要： This disclosure describes, in one embodiment, a network node element that includes a multi-lane port that includes a plurality of lanes for communication with at least one link partner; PHY circuitry including transmit circuitry and receive circuitry for each lane of the multi-lane port; and an auto-negotiations circuitry to transmit, during an auto-negotiation period of transmission between the network controller and the at least one link partner, a first base page on a first lane of the multi-lane port to the link partner, the first base page including a field for specifying a transmit NONCE sequence number and a field for identifying at least one PHY capability and at least one link width associated with the PHY circuitry; the auto-negotiations circuitry also to receive, during the auto-negotiation period, a second base page on at least one lane from the at least one link partner, the second base page including a field for specifying a field for specifying an echoed NONCE sequence number and a field for identifying at least one PHY capability and at least one link width associated with the link partner; and wherein the auto-negotiations circuitry to determine if the link partner includes a multi-lane port or at least one single-lane port based on, at least in part, the at least one PHY capability identified in the second base page and to resolve a multi-lane connection or a single-lane connection with the link partner based on, at least in part, the at least one PHY capability identified in the second base page.
摘要翻译：本公开在一个实施例中描述了一种网络节点元素，其包括多通道端口，该多通道端口包括用于与至少一个链路伙伴进行通信的多个通道; PHY电路包括多通道端口的每个通道的发射电路和接收电路; 以及自动协商电路，用于在所述网络控制器与所述至少一个链路伙伴之间的传输自动协商期间将所述多通道端口的第一通道上的第一基页发送到所述链路伙伴，所述第一基本页面，其包括用于指定发送NONCE序列号的字段和用于识别至少一个PHY能力的字段和与所述PHY电路相关联的至少一个链路宽度; 所述自动协商电路还在所述自动协商周期期间接收来自所述至少一个链路伙伴的至少一个通道上的第二基页，所述第二基页包括用于指定用于指定回送的NONCE序列的字段的字段数字和字段，用于识别至少一个PHY能力和与所述链路伙伴关联的至少一个链路宽度; 并且其中所述自动协商电路基于至少部分地基于在所述第二基页中标识的所述至少一个PHY能力来确定所述链路伙伴是否包括多通道端口或至少一个单通道端口，并且解决至少部分地基于第二基页中标识的至少一个PHY能力，与链路伙伴的多通道连接或单通道连接。

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