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1. 发明申请

WO2017091229A1 ELECTRICAL INTERCONNECT FOR A FLEXIBLE ELECTRONIC PACKAGE 审中-公开
标题翻译：用于柔性电子封装的电气互连
公开(公告)号：WO2017091229A1
公开(公告)日：2017-06-01
申请号：PCT/US2015/062720
申请日：2015-11-25
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson Chung Peng , HALL, Stephen H. , YONG, Khang Choong , OOI, Kooi Chi , GANTNER, Eric C.
IPC分类号： H05K1/02 , H05K1/11
CPC分类号： H05K1/0253 , H01L23/5387 , H05K1/0225 , H05K1/0245 , H05K1/189
摘要： An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.
摘要翻译：
电子封装的电气互连。电互连件包括第一电介质层; 第二电介质层; 信号导体，位于第一介电层和第二介电层之间; 以及安装在第一电介质层上的导电参考层，并且其中导电参考层不覆盖信号导体。导电参考层可以是第一导电参考层并且电互连还包括安装在第二电介质层上的第二导电参考层。第二导电参考层不覆盖信号导体。另外，信号导体可以是第一信号导体，并且电气互连件可以进一步包括在第一电介质层和第二电介质层之间的第二信号导体。第一和第二信号导体可以形成差分导体对。

2. 发明申请

WO2017052783A1 STRUCTURES FOR EDGE-TO-EDGE COUPLING WITH FLEXIBLE CIRCUITRY 审中-公开
标题翻译：具有柔性电路的边缘耦合结构
公开(公告)号：WO2017052783A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/045034
申请日：2016-08-01
申请人： INTEL CORPORATION
发明人： LI, Xiang , HALL, Stephen H.
IPC分类号： H01R12/77 , H01R12/79 , H01R12/88 , H05K1/14
CPC分类号： H01R12/79 , H01R12/728 , H01R12/732
摘要： Techniques and mechanisms for coupling a flexible circuit device to another device. In an embodiment, a substrate includes a first side and a second side opposite the first side, where first contacts of a hardware interface are disposed on the first side, and second contacts of the hardware interface are disposed on the second side. First interconnects and second interconnects variously extend in the substrate, where the first contacts are coupled via the first side each to a respective one of the first interconnects, and the second contacts are coupled via the second side each to a respective one of the second interconnects. In another embodiment, the substrate is one of a flexible substrate and a printed circuit board substrate, where the first interface is configured to couple the substrate, in an edge-to-edge configuration, with the other of a flexible substrate and a printed circuit board substrate.
摘要翻译：将柔性电路装置耦合到另一装置的技术和机构。在一个实施例中，基板包括与第一侧相对的第一侧和第二侧，硬件接口的第一触点设置在第一侧上，并且硬件接口的第二触点设置在第二侧上。第一互连和第二互连在衬底中不同地延伸，其中第一触点经由第一侧经由第一侧耦合到第一互连中的相应一个，并且第二触点经由第二侧耦合到相应的第二互连。在另一个实施例中，衬底是柔性衬底和印刷电路板衬底之一，其中第一界面被配置为以边缘对边缘构造将柔性衬底和印刷电路中的另一个耦合到衬底板基板。

3. 发明申请

WO2018063416A1 MUTUAL INDUCTANCE SUPPRESSOR FOR CROSSTALK IMMUNITY ENHANCEMENT 审中-公开
标题翻译：用于串扰抗扰度增强的互感抑制器
公开(公告)号：WO2018063416A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/055083
申请日：2016-10-01
申请人： INTEL CORPORATION
发明人： YONG, Khang Choong , KONG, Jackson Chung Peng , CHEAH, Bok Eng , HALL, Stephen H.
IPC分类号： H05K1/02 , H05K1/18
摘要： Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.
摘要翻译：实施例通常针对用于增强串扰免疫性的互感抑制器。印刷电路板的实施例包括第一层上的第一信号迹线和第二信号迹线，其中第一信号迹线和第二信号迹线不相交; 在所述第一层下方的第二层，所述第二层包括电压参考平面; 以及所述电压参考平面中的互感抑制器，所述互感抑制器包括所述第一信号迹线和所述第二信号迹线之间的电压参考平面的蛇形部分。

4. 发明申请

WO2018063380A1 MULTIPLE-LAYER, SELF-EQUALIZING INTERCONNECTS IN PACKAGE SUBSTRATES 审中-公开
标题翻译：封装基板中的多层自平衡互连
公开(公告)号：WO2018063380A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054939
申请日：2016-09-30
申请人： INTEL CORPORATION , HALL, Stephen H. , CHEAH, Bok Eng , SREERAMA, Chaitanya , KONG, Jackson Chung Peng
发明人： HALL, Stephen H. , CHEAH, Bok Eng , SREERAMA, Chaitanya , KONG, Jackson Chung Peng
IPC分类号： H01L23/00 , H01L23/12
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/498 , H01L23/49811 , H01L23/49866 , H01L23/66
摘要： A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.
摘要翻译：
连接器中的自动均衡互连器安装在微电子器件中。自动均衡互连由多个导电层形成，以在运行期间抵消与频率变化相关的趋肤效应损失。每个连续的层被配置为具有次高的导电率，随后的导电膜的电导率逐渐降低。在一个实施例中，邻近参考平面的导电膜的厚度被构造得最薄并且随后的膜被添加并且逐渐地逐渐变厚。最高导电膜被配置为最接近连接器中的参考平面，并且最低导电膜离基准平面最远。

5. 发明申请

WO2017172203A1 FLEXIBLE PRINTED CIRCUIT EMI ENCLOSURE 审中-公开
标题翻译：柔性印刷电路EMI外壳
公开(公告)号：WO2017172203A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020147
申请日：2017-03-01
申请人： INTEL CORPORATION
发明人： YONG, Khang Choong , HALL, Stephen H. , CHUAH, Tin Poay , KOH, Boon Ping , GOH, Eng Huat
IPC分类号： H05K9/00
CPC分类号： H05K1/147 , G06K9/0002 , H01L25/18 , H05K1/0218 , H05K1/181 , H05K3/363 , H05K9/0024 , H05K2201/047 , H05K2201/056 , H05K2201/10159
摘要： Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.
摘要翻译：三维（3-D）体积电路板架构设计为面向电路板小型化的技术问题提供技术解决方案。三维立体体系结构包括在垂直维度中使用更多未使用的体积（例如，Z维度）以增加总电路板体积的利用率。三维体积架构是通过将组件安装在第一PCB和第二PCB上以及倒置并悬挂第一PCB上方的第二PCB来实现的。使用3D体积电路板架构设计可以进一步形成屏蔽FEMIE，从而提供屏蔽和改进的体积使用，而系统性能几乎没有降低或系统Z高度增加。

6. 发明申请

WO2014105173A1 CROSSTALK AWARE ENCODING FOR A DATA BUS 审中-公开
标题翻译： CROSSTALK AWARE编码数据总线
公开(公告)号：WO2014105173A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047642
申请日：2013-06-25
申请人： INTEL CORPORATION , HALL, Stephen H. , SREERAMA, Chaitanya , MIX, Jason, A. , LEDDIGE, Michael, W. , SANCHEZ SANCHEZ, Jose, A. , OLUWAFEMI, Olufemi, B. , HURAY, Paul, G. , FALCONER, Maynard, C.
发明人： HALL, Stephen H. , SREERAMA, Chaitanya , MIX, Jason, A. , LEDDIGE, Michael, W. , SANCHEZ SANCHEZ, Jose, A. , OLUWAFEMI, Olufemi, B. , HURAY, Paul, G. , FALCONER, Maynard, C.
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/4022
摘要： Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs.
摘要翻译：本文描述了用于编码数据的技术。根据本技术的设备的示例包括耦合到多个数字输入的信令模块。信令模块是对在多个数字输入端接收到的数据进行编码，以生成编码数据。基于编码数据，信令模块可以驱动总线的多个信号线上的线路电压。多个线路电压中的每一个对应于在多个数字输入端接收的数据的加权和。

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