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1. 发明申请

WO2016105400A1 DECOUPLED VIA FILL 审中-公开
标题翻译：通过填写
公开(公告)号：WO2016105400A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072249
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： SHUSTERMAN, Yuriy V. , GRIGGIO, Flavio , INDUKURI, Tejaswi K. , BRAIN, Ruth A.
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/203
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32133 , H01L21/76847 , H01L23/3171 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266
摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.
摘要翻译：公开了用于提供去耦通孔填充物的技术。给定通孔，第一阻挡层保形地沉积在沟槽的底部和侧壁上。第一金属填充物被覆盖地沉积到沟槽中。随后凹入非选择性沉积，使得只有一部分沟槽被第一金属填充。先前沉积的第一阻挡层与第一金属一起被去除，从而再次暴露沟槽的上侧壁。第二阻挡层保形地沉积在第一金属的顶部上和现在再暴露的沟槽侧壁上。第二个金属填充物被覆盖地沉积到剩余的沟槽中。平面化和/或蚀刻可以根据需要进行后续处理。因此，提供了使用双金属工艺填充高纵横比孔的方法。但是，注意，第一和第二填充金属可以是相同的。

2. 发明申请

WO2017111820A1 REDUCED HEIGHT LINER FOR INTERCONNECTS 审中-公开
标题翻译：互连的降低高度衬垫
公开(公告)号：WO2017111820A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000378
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： CHOWDHURY, Akm Shaestagir , GRIGGIO, Flavio
IPC分类号： H01L21/768 , H01L21/60
CPC分类号： H01L21/76879 , H01L21/288 , H01L21/76843 , H01L21/76865 , H01L23/53223 , H01L23/53266
摘要： An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening, in the dielectric layer, (a) having sidewalls and an aspect ratio of at least 5:1 (height: width), and (b) exposing a conductive region of at least one of the substrate and an additional interconnect structure; a conformal thin film layer on the sidewalls; and a polycrystalline metal within the opening and on the thin film layer; wherein the thin film layer forms an adhesive liner that extends only partially up the sidewalls leaving upper portions of the sidewalls uncovered by the liner. Other embodiments are described herein.
摘要翻译：一个实施例包括金属互连结构，该金属互连结构包括：在衬底上的电介质层; （a）具有至少5：1（高度：宽度）的侧壁和高宽比的开口，以及（b）暴露基板和附加互连结构中的至少一个的导电区域; 在侧壁上的共形薄膜层; 以及在所述开口内和所述薄膜层上的多晶金属; 其中所述薄膜层形成仅部分地延伸到所述侧壁上方的粘合剂衬里，留下未被所述衬里覆盖的所述侧壁的上部。这里描述了其他实施例。

3. 发明申请

WO2017087005A1 METALLIZATION STACKS WITH ENCLOSED VIAS 审中-公开
标题翻译：具有封闭式VIAS的金属化堆叠
公开(公告)号：WO2017087005A1
公开(公告)日：2017-05-26
申请号：PCT/US2015/062031
申请日：2015-11-21
申请人： INTEL CORPORATION
发明人： GRIGGIO, Flavio , INDUKURI, Tejaswi K.
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/48 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/08 , H01L24/16 , H01L24/20 , H01L25/03 , H01L25/0657 , H01L2224/08235 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2225/06572 , H01L2924/1434
摘要： Described herein are systems and methods for providing a metallization stack to be used in an integrated circuit (IC) package. The metallization stack includes a via for providing electrical interconnection between a first interconnect and a second interconnect. The via is isolated from each of the first and the second interconnects by a respective barrier layer of an electrically conductive material. Enclosing the via from the interconnects using barrier layers reduces electromigration due to interdiffusion of the materials filling each of the interconnects and the material filling the via. Furthermore, such decoupling the via from the interconnects may allow the use of scaled thin conformal barriers for the interconnects and via, thus improving interconnect resistance, via resistance, and/or RC performance of the interconnect.
摘要翻译：这里描述的是用于提供要在集成电路（IC）封装中使用的金属化叠层的系统和方法。金属化叠层包括用于提供第一互连和第二互连之间的电互连的通孔。通孔通过导电材料的相应阻挡层与第一互连和第二互连中的每一个隔离。使用阻挡层从互连封装通孔减少了由于填充每个互连的材料和填充通孔的材料的相互扩散而导致的电迁移。此外，将通孔与互连分开的这种解耦允许使用缩放的薄共形势垒用于互连和通孔，从而改善互连的电阻，通孔电阻和/或RC性能。

4. 发明申请

WO2016204771A1 BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：用于半导体结构的金属特征的底部填充（BUF）
公开(公告)号：WO2016204771A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036519
申请日：2015-06-18
申请人： INTEL CORPORATION
发明人： CLENDENNING, Scott B. , MITAN, Martin M. , GLASSMAN, Timothy E. , GRIGGIO, Flavio , KLOSTER, Grant M. , FRASURE, Kent N. , GSTREIN, Florian , HOURANI, Rami
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76879 , C23C16/045 , H01L21/28 , H01L21/28556 , H01L21/28562 , H01L21/31144 , H01L21/76843 , H01L21/76861 , H01L21/76865 , H01L21/76876 , H01L29/66545 , H01L29/66795 , H01L2221/1063
摘要： Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.
摘要翻译：描述了用于形成半导体结构的金属特征的自底向上填充方法以及所得的结构。在一个示例中，半导体结构包括设置在层间电介质（ILD）层中的沟槽。沟槽有侧壁，底部和顶部。 U形金属种子层设置在沟槽的底部并且沿着沟槽的侧壁但基本上在沟槽的顶部下方。金属填充层设置在U形金属种子层上，并将沟槽填充到沟槽的顶部。金属填充层与U形金属种子层上方的沟槽的侧壁的部分直接接触ILD层的电介质材料。

5. 发明申请

WO2018190817A1 INTEGRATED CIRCUIT INTERCONNECTS 审中-公开
公开(公告)号：WO2018190817A1
公开(公告)日：2018-10-18
申请号：PCT/US2017/027108
申请日：2017-04-12
申请人： INTEL CORPORATION
发明人： ZIERATH, Daniel J. , GRIGGIO, Flavio , BROOKS, John D.
IPC分类号： H01L21/768
摘要： Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.

6. 发明申请

WO2016195672A1 THE USE OF NOBLE METALS IN THE FORMATION OF CONDUCTIVE CONNECTORS 审中-公开
标题翻译：贵金属在形成导电连接器中的应用
公开(公告)号：WO2016195672A1
公开(公告)日：2016-12-08
申请号：PCT/US2015/033930
申请日：2015-06-03
申请人： INTEL CORPORATION , JEZEWSKI, Christopher, J. , MUKHERJEE, Srijit , BERGSTROM, Daniel, B. , INDUKURI, Tejaswi, K. , GRIGGIO, Flavio , CHEBIAM, Ramanan, V. , CLARKE, James, S.
发明人： JEZEWSKI, Christopher, J. , MUKHERJEE, Srijit , BERGSTROM, Daniel, B. , INDUKURI, Tejaswi, K. , GRIGGIO, Flavio , CHEBIAM, Ramanan, V. , CLARKE, James, S.
IPC分类号： H01L21/3205
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/5226 , H01L23/53252 , H01L23/53266
摘要： In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.
摘要翻译：在一个实施例中，用于微电子部件的导电连接器可以形成有设置在阻挡衬里和导电填充材料之间的用作粘附/润湿层的贵金属层。在另一实施例中，导电连接器可以具有直接设置在阻挡衬里上的贵金属导电填充材料。使用贵金属作为粘合/润湿层或作为导电填充材料可以改善间隙填充和粘附，这可能导致导电连接器基本上没有空隙，从而改善导电连接器相对于导电连接器的电性能没有贵金属作为粘附/润湿层或导电填料。

7. 发明申请

WO2018125069A1 METHODS OF FORMING SUBSTRATE INTERCONNECT STRUCTURES FOR ENHANCED THIN SEED CONDUCTION 审中-公开
公开(公告)号：WO2018125069A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068798
申请日：2016-12-28
申请人： INTEL CORPORATION
发明人： JEZEWSKI, Christopher J. , CHALUPA, Radek P. , GRIGGIO, Flavio , MERIC, Inanc , YANG, Jiun-Chan
IPC分类号： H01L21/20 , H01L21/203 , H01L21/02
CPC分类号： H01L23/522 , C23C18/1653 , C23C18/38 , C25D7/123 , H01L21/76873 , H01L23/485 , H01L23/585
摘要： Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.

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