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1. 发明申请

WO2017165041A1 TECHNOLOGIES FOR MEMORY MANAGEMENT OF NEURAL NETWORKS WITH SPARSE CONNECTIVITY 审中-公开
标题翻译：具有稀疏连通性的神经网络存储器管理技术
公开(公告)号：WO2017165041A1
公开(公告)日：2017-09-28
申请号：PCT/US2017/018662
申请日：2017-02-21
申请人： INTEL CORPORATION
发明人： PAUL, Somnath , AUGUSTINE, Charles , KHELLAH, Muhammad M. , SHEIK, Sadique Ul Ameen
IPC分类号： G06N3/06 , G06F12/02
摘要： Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.
摘要翻译：用于神经网络的存储器管理的技术包括：计算装置读取计算装置的存储器以访问与神经网络的神经元相关联的连接性数据;确定存储器地址，在该存储器地址处，与存储一个或多个网络连接，并从与存储器地址对应的存储器位置访问相应的权重。连接数据表示来自神经元的一个或多个网络连接。

2. 发明申请

WO2016171788A1 BITCELL STATE RETENTION 审中-公开
标题翻译： BITCELL州保留
公开(公告)号：WO2016171788A1
公开(公告)日：2016-10-27
申请号：PCT/US2016/018800
申请日：2016-02-19
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , TOMISHIMA, Shigeki , TSCHANZ, James W. , LU, Shih-Lien L.
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1659 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
摘要翻译：根据本公开的各种实施例，描述了诸如自旋传递转矩（STT）随机存取存储器（RAM），STTRAM的MRAM存储器中的杂散磁场减轻。在一个实施例中，可以通过产生磁场来补偿可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。在另一个实施例中，可以通过选择性地暂停对一行存储器的访问来临时终止可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。本文描述了其它方面。

3. 发明申请

WO2015134037A1 PHYSICALLY UNCLONABLE FUNCTION CIRCUIT USING RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：使用电阻式存储器件的物理不可靠功能电路
公开(公告)号：WO2015134037A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/021696
申请日：2014-03-07
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , TOKUNAGA, Carlos , TSCHANZ, James W.
IPC分类号： G11C7/24
CPC分类号： G11C11/1695 , G06F21/34 , G06F21/73 , G06F21/79 , G09C1/00 , G11C7/16 , G11C7/24 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C2013/0045 , G11C2013/005 , H03M1/12 , H03M1/124 , H04L9/0866
摘要： Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
摘要翻译：描述了一种物理上不可克隆的功能电路，包括：具有至少两个端子的电阻式存储器件（例如，MTJ器件）耦合到电阻式存储器件的至少两个端子之一的晶体管; 以及模数转换器（ADC），其具有耦合到所述电阻性存储器件的至少两个端子中的一个的输入。

4. 发明申请

WO2019245687A1 A HIGH DENSITY NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
公开(公告)号：WO2019245687A1
公开(公告)日：2019-12-26
申请号：PCT/US2019/033170
申请日：2019-05-20
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , KUO, Charles C. , CHU-KUNG, Benjamin , KHELLAH, Muhammad M.
IPC分类号： G11C11/38 , G11C11/413
摘要： Described is an apparatus which comprises: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR); a third device coupled to a second reference and the storage node, wherein the third device has NDR; and a circuitry for reading data, the circuitry coupled to the storage node and the first, second, and third devices, wherein the first, second, and third devices, and the circuitry are positioned in a backend-of-line (BEOL) of a die.

5. 发明申请

WO2018182709A1 CIRCUITS WITH ENHANCED CURRENT PEAK TO VALLEY CURRENT RATIO 审中-公开
公开(公告)号：WO2018182709A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025486
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： CHU-KUNG, Benjamin , KUO, Charles C. , DOYLE, Brian S. , AUGUSTINE, Charles
IPC分类号： H03K17/30 , H03K17/74
CPC分类号： G11C11/411 , G11C11/38
摘要： Negative differential resistance (NDR) can be used in connection with memory circuits and/or devices. The performance of such a memory switch can be related to the peak to valley current ratio of the current through the memory switch. A higher current peak to valley current ratio can imply a more robust memory switch. In one embodiment, a circuit is described that generally operates by taking the output of a NDR exhibiting circuit including a resonant tunneling diode (RTD) and a first bipolar junction transistor (BJT) through a second BJT to generate current voltage characteristics having high current peak to valley current ratios; further the base current of the first BJT can be used to reduce the outputted valley current of the circuit.

6. 发明申请

WO2018125173A1 ON-DIE ISOLATION INTEGRITY DETERMINATION 审中-公开
公开(公告)号：WO2018125173A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069350
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： KUMAR, Suriya Kumar Ashok , KASIM, Rahim , AUGUSTINE, Charles , LAKAMRAJU, Narendra V. , GILL, Balkaran Singh
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R31/129 , G01R31/2856 , G01R31/2896
摘要： Herein described are apparatuses, systems, and methods for testing dielectric isolation. A semiconductor package may include a device under test (DUT). The DUT may have a first conductive element and a second conductive element, the first conductive element isolated from the second conductive element by a dielectric material. The semiconductor package may further include measurement circuitry coupled to the DUT. The measurement circuitry may apply an initial voltage to the DUT, the initial voltage applied to the first conductive element, and may couple the second conductive element to ground. The measurement circuitry may further determine a time period of discharge for the first conductive element to discharge to a threshold voltage from the initial voltage, and determine an integrity of dielectric isolation between the first conductive element and the second conductive element based on the time period of discharge.

7. 发明申请

WO2017052729A1 ELECTRONIC NEURAL NETWORK CIRCUIT HAVING A RESISTANCE BASED LEARNING RULE CIRCUIT 审中-公开
标题翻译：具有电阻的学习电路的电子神经网络电路
公开(公告)号：WO2017052729A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/042839
申请日：2016-07-18
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , PAUL, Somnath
IPC分类号： G06N3/08
CPC分类号： G06N3/08 , G06N3/04 , G06N3/049 , G06N3/063
摘要： An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes spiking neural network circuitry. The spiking neural network circuitry includes a learning rule circuit. The learning rule circuit includes a resistive element. A resistance of the resistive element is to determine a change in a weight of a synapse between neurons of the spiking neural network circuitry.
摘要翻译：描述了一种装置。该装置包括半导体芯片。半导体芯片包括尖峰神经网络电路。刺激神经网络电路包括学习规则电路。学习规则电路包括电阻元件。电阻元件的电阻是确定尖峰神经网络电路的神经元之间突触重量的变化。

8. 发明申请

WO2018125463A1 FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS 审中-公开
公开(公告)号：WO2018125463A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063448
申请日：2017-11-28
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , RIOS, Rafael , PAUL, Somnath , KHELLAH, Muhammad M.
IPC分类号： H03K3/037 , H03K3/356 , H03K3/012
摘要： Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

9. 发明申请

WO2018071333A1 HYBRID COMPRESSION SCHEME FOR EFFICIENT STORAGE OF SYNAPTIC WEIGHTS IN HARDWARE NEUROMORPHIC CORES 审中-公开
标题翻译：复杂压缩方案有效存储硬度神经形核中突触权重
公开(公告)号：WO2018071333A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/055755
申请日：2017-10-09
申请人： INTEL CORPORATION
发明人： PAUL, Somnath , AUGUSTINE, Charles , KHELLAH, Muhammad, M.
IPC分类号： G06N3/063
摘要： Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.
摘要翻译：系统，设备和方法可以提供混合压缩方案以将神经形态核心中的突触权重存储。混合压缩方案利用游程长度编码（RLE）压缩方法，基于字典的编码压缩方案和无压缩编码方案来存储突触权重存储器中的有效突触连接的权重。

10. 发明申请

WO2018057896A1 A NEUROMORPHIC COMPUTING DEVICE, MEMORY DEVICE, SYSTEM, AND METHOD TO MAINTAIN A SPIKE HISTORY FOR NEURONS IN A NEUROMORPHIC COMPUTING ENVIRONMENT 审中-公开
标题翻译：一种神经形态计算装置，存储装置，系统和方法，用于在神经形态计算环境中维持神经元的刺激历史
公开(公告)号：WO2018057896A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/052965
申请日：2017-09-22
申请人： INTEL CORPORATION
发明人： WU, Wei , AUGUSTINE, Charles , PAUL, Somnath
IPC分类号： G06N3/063 , G11C11/413
摘要： Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.
摘要翻译：提供了一种神经形态计算设备，存储设备，系统和方法，用于维持尖峰神经网络中的神经元的尖峰历史。在具有存储器单元的行和列的阵列的存储器装置中产生神经网络尖峰历史。针对多个时隙中的每一个的多个神经元和列中的每一个存在一行的行。在发射峰值的发射神经元的存储器单元的行中的当前列中进行指示。在当前列中指示闲置神经元的存储器单元行中没有触发尖峰未被触发的指示。阵列中的信息用于确定连接的神经元和发射神经元之间的时间差，并调整连接突触的重量。

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