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1. 发明申请

WO0231878A3 TRENCH CAPACITOR DRAM PROCESS WITH PROTECTED TOP OXIDE DURING STI ETCH 审中-公开
标题翻译：在STI蚀刻期间具有保护的顶部氧化物的TRENCH电容器DRAM工艺
公开(公告)号：WO0231878A3
公开(公告)日：2002-10-31
申请号：PCT/US0126644
申请日：2001-08-24
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： JAIPRAKASH VENKATACHALAN , MANDELMAN JACK , DIVAKARUNI RAMACHANDRAR , MALIK RAJEEV , SEITZ MIHEL
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： An array top oxide is protected in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays by a protective etch stop layer (18) which protects the top oxide (16) and prevents word line to substrate shorts and/or leakage. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor polysilicon (17) of the vertical MOSFET to the top surface of the top oxide (16). A thin polysilicon layer (18) is deposited over the planarized surface and an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches (20).
摘要翻译：在通过保护顶部氧化物（16）的保护性蚀刻停止层（18）制造垂直金属氧化物半导体场效应晶体管（MOSFET）动态随机存取存储器（DRAM）阵列中的阵列顶部氧化物被保护，并且防止字线衬底短路和/或泄漏。包括垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体多晶硅（17）平坦化到顶部氧化物（16）的顶表面进行。在平坦化表面上沉积薄多晶硅层（18），并沉积有源区（AA）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。使用AA掩模将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽（20）。

2. 发明申请

WO0198563A3 ORIENTATION INDEPENDENT OXIDATION OF SILICON 审中-公开
标题翻译：方向独立氧化硅
公开(公告)号：WO0198563A3
公开(公告)日：2002-05-30
申请号：PCT/US0119077
申请日：2001-06-14
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： TEWS HELMUT HORST , FALTERMEIR JOHNATHAN E , MALIK RAJEEV , HEENAN CAROL , GLUSCHENKOV OLEG
IPC分类号： C30B29/06 , C30B33/00 , H01L21/28 , H01L21/316 , H01L21/762 , H01L29/51
CPC分类号： H01L21/28185 , C30B29/06 , C30B33/00 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28176 , H01L21/28211 , H01L21/31662 , H01L21/76202 , H01L29/513 , H01L29/518 , Y10S438/973
摘要： A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate (step 100) where surfaces have at least two different crystallographic orientations of the silicon crystal (step 102). Atomic oxygen (O) is formed for oxidizing the surfaces (step 106). An oxide is formed (step 108) on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.
摘要翻译：根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中表面具有硅晶体的至少两个不同晶体取向的衬底（步骤100）（步骤102 ）。形成氧化表面的原子氧（O）（步骤106）。通过使原子氧与表面反应，在表面上形成氧化物（步骤108），同时在表面上形成基本均匀的氧化物厚度。

3. 发明申请

WO2006063060A3 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 审中-公开
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：WO2006063060A3
公开(公告)日：2006-11-16
申请号：PCT/US2005044281
申请日：2005-12-08
申请人： IBM , CHIDAMBARRAO DURESETI , LI YING , MALIK RAJEEV , NARASIMHA SHREESH , YANG HAINING , ZHU HUILONG
发明人： CHIDAMBARRAO DURESETI , LI YING , MALIK RAJEEV , NARASIMHA SHREESH , YANG HAINING , ZHU HUILONG
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370），其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

4. 发明申请

WO2004027824A2 NITRIDE AND POLYSILICON INTERFACE WITH TITANIUM LAYER 审中-公开
标题翻译：氮化钛和多晶硅界面与钛层
公开(公告)号：WO2004027824A2
公开(公告)日：2004-04-01
申请号：PCT/US0329085
申请日：2003-09-16
申请人： INFINEON TECHNOLOGIES AG , IBM , SCHUTZ RONALD J , ROBL WERNER , MALIK RAJEEV , CLEVENGER LARRY , GLUSCHENKOV OLEG , CABRAL CYRIL JR , IGGULDEN ROY C , WANG YUN-YU , WONG KWONG HON , MCSTAY IRENE
发明人： SCHUTZ RONALD J , ROBL WERNER , MALIK RAJEEV , CLEVENGER LARRY , GLUSCHENKOV OLEG , CABRAL CYRIL JR , IGGULDEN ROY C , WANG YUN-YU , WONG KWONG HON , MCSTAY IRENE
IPC分类号： H01L20060101 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L29/40 , H01L29/51 , H01L29/78 , H01L
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34）在氮化钨层上形成含钨层和钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

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