专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005004162A2 CROSS-POINT MRAM ARRAY WITH REDUCED VOLTAGE DROP ACROSS MTJ'S 审中-公开
标题翻译：具有降低电压降的跨点MRAM阵列
公开(公告)号：WO2005004162A2
公开(公告)日：2005-01-13
申请号：PCT/EP2004/006190
申请日：2004-06-08
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION , DEBROSSE, John , LAMMERS, Stefan , VIEHMANN, Hans-Heinrich
发明人： DEBROSSE, John , LAMMERS, Stefan , VIEHMANN, Hans-Heinrich
IPC分类号： G11C11/16
CPC分类号： G11C11/15
摘要： A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.
摘要翻译：一种在交叉点磁存储器阵列和交叉点磁存储器件结构中存储信息的方法。在写入操作期间，磁隧道结（MTJ）的电压降最小化，以防止损坏阵列的MTJ。在写操作期间，所选MTJ，未选MTJ或两者的电压降最小化，减少了MTJ的压力，减少了泄漏电流，降低了功耗并增加了写入裕度。

2. 发明申请

WO2004107348A1 CIRCUIT CONFIGURATION FOR A CURRENT SWITCH OF A BIT/WORD LINE OF A MRAM DEVICE 审中-公开
标题翻译： MRAM器件的位/字线的电流开关的电路配置
公开(公告)号：WO2004107348A1
公开(公告)日：2004-12-09
申请号：PCT/EP2004/005675
申请日：2004-05-26
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION , DEBROSSE, John , VIEHMANN, Hans-Heinrich
发明人： DEBROSSE, John , VIEHMANN, Hans-Heinrich
IPC分类号： G11C11/15
CPC分类号： G11C11/16 , G11C7/12 , G11C8/08
摘要： A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.
摘要翻译：一种用于磁阻随机存取存储器（MRAM）器件的位线或字线的电流开关的电路配置，包括定向开关和电压驱动器，其在操作中降低了方向开关的导通电阻。在一个实施例中，线路的每个终端设置有这样的开关。

3. 发明申请

WO2004112048A2 ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁阻随机访问存储器中的错误检测和校正方法和装置
公开(公告)号：WO2004112048A2
公开(公告)日：2004-12-23
申请号：PCT/EP2004/006019
申请日：2004-06-03
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION , DEBROSSE, John , HOENIGSCHMID, Heinz , LEUSCHNER, Rainer , MÜLLER, Gerhard
发明人： DEBROSSE, John , HOENIGSCHMID, Heinz , LEUSCHNER, Rainer , MÜLLER, Gerhard
IPC分类号： G11C29/00
CPC分类号： G11C7/24 , G06F11/106 , G11C11/406
摘要： The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.
摘要翻译：本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。此后，读出数据位和ECC校验位，并检测和校正任何错误。然后基于计数和数据位启动数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关联的ECC校验位，并且最终通过检查，校正和恢复数据位并将ECC校验位存储到存储区域。

4. 发明申请

WO2012005758A1 SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN THE BIT LINES 审中-公开
标题翻译：共享位线SMT MRAM阵列与位线之间的分束晶体管
公开(公告)号：WO2012005758A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/001157
申请日：2011-06-28
申请人： MAGIC TECHNOLOGIES, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Hsu, Kai , NAKAMURA, Yutaka , DEBROSSE, John
发明人： YANG, Hsu, Kai , NAKAMURA, Yutaka , DEBROSSE, John
IPC分类号： G11C5/08
CPC分类号： G11C11/1653 , G11C7/18 , G11C11/161 , G11C11/1655 , G11C11/1675
摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻，以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

5. 发明申请

WO2004040580A1 MAGNETIC TUNNEL JUNCTION MEMORY CELL ARCHITECTURE 审中-公开
标题翻译：磁性隧道接口存储单元架构
公开(公告)号：WO2004040580A1
公开(公告)日：2004-05-13
申请号：PCT/EP2003/011953
申请日：2003-10-28
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： DEBROSSE, John , GOGL, Dietmar , HOENIGSCHMID, Heinz
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16
摘要： A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure (114) and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure (104). In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch (106) is connected to the conductor (110) associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.
摘要翻译：存储器件包括具有磁性隧道结结构（114）和读取开关的磁性隧道结存储单元。在一个示例中，读取开关连接到用于写入磁性隧道结结构（104）的导体。在另一示例中，读开关是通过深通孔接触电耦合到磁隧道结结构的晶体管。在另一示例中，存储器件包括多个磁性隧道结存储器单元和分别与单元相关联的多个导体，用于将信息写入相关联的磁性隧道结结构。每个读取开关（106）连接到与除了读取开关所在的单元之外的磁性隧道结单元相关联的导体（110）。

6. 发明申请

WO2004057619A1 CURRENT SENSE AMPLIFIER 审中-公开
标题翻译：电流检测放大器
公开(公告)号：WO2004057619A1
公开(公告)日：2004-07-08
申请号：PCT/EP2003/014420
申请日：2003-12-17
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： DEBROSSE, John , GOGL, Dietmar , REOHR, William, Robert
IPC分类号： G11C7/06
CPC分类号： G11C7/067 , G11C2207/063
摘要： A symmetrical high-speed current sense amplifier (44) having complementary reference cells and configurable load devices (42) that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier (44) is adapted for use in a symmetric sensing architecture and includes a configurable current mirror (36). The current sense amplifier includes a voltage comparator (34), a first clamping device (T1) coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clampling device (T2) is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. A current mirror (36) is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the current mirror may be hard-wired, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads (42) may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator (T4), and between the first input signal and the second input signal (T3).
摘要翻译：具有互补参考单元和可配置负载设备（42）的对称高速电流检测放大器（44），其消除了架构相关的电容失配贡献。电流感测放大器（44）适于在对称感测架构中使用并且包括可配置电流镜（36）。电流感测放大器包括电压比较器（34），耦合在电压比较器的第一输入端和第一输入信号之间的第一钳位装置（T1），第一钳位装置耦合到参考电压。第二取样装置（T2）耦合在电压比较器的第二输入端和第二输入信号之间，第二钳位装置耦合到参考电压。电流镜（36）耦合在电压比较器的第一和第二输入端之间。电流镜可以通过选择晶体管来配置。或者，电流镜可以是硬连线的，并且可以使用多路复用器来选择第一输入信号还是第二输入信号连接到电流镜的第一或第二侧。可以在适当的节点添加可配置的虚拟负载（42），以优化容性负载并增加放大器的速度。均衡装置可以耦合在电压比较器（T4）的第一和第二输入端之间以及在第一输入信号和第二输入信号（T3）之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式