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1. 发明申请

WO0250842A3 METHOD FOR READING OUT OR IN A STATUS FROM OR TO A FERROELECTRICAL TRANSISTOR OF A MEMORY CELL AND MEMORY MATRIX 审中-公开
标题翻译：用于从一个或一个存储器单元的铁电晶体读取和存储条件的方法以及存储器存储器
公开(公告)号：WO0250842A3
公开(公告)日：2002-12-27
申请号：PCT/DE0104785
申请日：2001-12-19
申请人： INFINEON TECHNOLOGIES AG , GOEBEL HOLGER , HOENIGSCHMID HEINZ , HOENLEIN WOLFGANG , HANEDER THOMAS , ULLMANN MARC
发明人： GOEBEL HOLGER , HOENIGSCHMID HEINZ , HOENLEIN WOLFGANG , HANEDER THOMAS , ULLMANN MARC
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , Y10S977/943
摘要： The status is read out from or stored in the ferroelectrical transistor. During the reading out or storing of the status, at least one further ferroelectrical transistor in the memory matrix is controlled such as to be operated in the depletion region thereof.
摘要翻译：该状态从铁电晶体管读出或存储在铁电晶体管中。在读取或存储状态期间，存储器矩阵中的至少一个另外的铁电晶体管被驱动，使得其在其耗尽区中操作。

2. 发明申请

WO0239455A2 MRAM ARRANGEMENT WITH SELECTION TRANSISTORS OF LARGE CHANNEL WIDTH 审中-公开
标题翻译：具有大通道宽度选择晶体管的MRAM安排
公开(公告)号：WO0239455A2
公开(公告)日：2002-05-16
申请号：PCT/DE0104232
申请日：2001-11-12
申请人： INFINEON TECHNOLOGIES AG , BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
发明人： BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.
摘要翻译：本发明涉及一种MRAM装置，其中选择晶体管（T）被分配给多个MTJ存储单元（1）并且具有增加的沟道宽度。

3. 发明申请

WO0249035A3 MEMORY DEVICE AND METHOD FOR THE OPERATION OF THE SAME 审中-公开
标题翻译：存储设备与方法进行操作
公开(公告)号：WO0249035A3
公开(公告)日：2003-01-23
申请号：PCT/DE0104524
申请日：2001-12-03
申请人： INFINEON TECHNOLOGIES AG , HOENIGSCHMID HEINZ , MUELLER GERHARD
发明人： HOENIGSCHMID HEINZ , MUELLER GERHARD
IPC分类号： G11C8/02 , G11C11/15 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L27/115
CPC分类号： G11C11/22
摘要： The aim of the invention is to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate conduction device (50) of a memory device (1) which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor (10) and hence, the information that is stored.
摘要翻译：为了确保高的灵活性和紧凑的结构的现有的板线装置（50），用于检测一个存储电容器（10），从而所存储的信息的状态时，它在存储装置（1），其滞后工艺以形成的基础上操作，提出了

4. 发明申请

WO0239454A3 MAGNETORESISTIVE MEMORY (MRAM) 审中-公开
标题翻译：磁阻存储器（MRAM）
公开(公告)号：WO0239454A3
公开(公告)日：2002-12-19
申请号：PCT/EP0112622
申请日：2001-10-31
申请人： INFINEON TECHNOLOGIES AG , FREITAG MARTIN , HOENIGSCHMID HEINZ , GOGL DIETMAR , LAMMERS STEFAN
发明人： FREITAG MARTIN , HOENIGSCHMID HEINZ , GOGL DIETMAR , LAMMERS STEFAN
IPC分类号： H01L27/105 , G11C11/16 , H01L21/8246 , H01L27/22 , H01L43/08 , G11C11/15
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16
摘要： The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.
摘要翻译：从列和行的矩阵一个建成的引线的形状导致的多个磁存储单元的单元阵列被偏离引线的方形横截面的优化，使得磁场分量从交叉点Bx的随着距离的增加躺在单元阵列平面中的写电流的足够快地降低。

5. 发明申请

WO2004112048A3 ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁阻随机访问存储器中的错误检测和校正方法和装置
公开(公告)号：WO2004112048A3
公开(公告)日：2005-04-07
申请号：PCT/EP2004006019
申请日：2004-06-03
申请人： INFINEON TECHNOLOGIES AG , IBM , DEBROSSE JOHN , HOENIGSCHMID HEINZ , LEUSCHNER RAINER , MUELLER GERHARD
发明人： DEBROSSE JOHN , HOENIGSCHMID HEINZ , LEUSCHNER RAINER , MUELLER GERHARD
IPC分类号： G06F11/10 , G11C7/24 , G11C11/406 , G11C29/00 , G11C11/15
CPC分类号： G11C7/24 , G06F11/106 , G11C11/406
摘要： The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.
摘要翻译：本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。此后，读出数据位和ECC校验位，并检测和校正任何错误。然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位并将ECC校验位存储到存储区域。

6. 发明申请

WO0239455A8 MRAM ARRANGEMENT WITH SELECTION TRANSISTORS OF LARGE CHANNEL WIDTH 审中-公开
公开(公告)号：WO0239455A8
公开(公告)日：2002-10-17
申请号：PCT/DE0104232
申请日：2001-11-12
申请人： INFINEON TECHNOLOGIES AG , BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
发明人： BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.

7. 发明申请

WO0127974A3 DRAM WITH BIT LINES IN TWO METALLISED SHEETS 审中-公开
标题翻译：在两个金属与DRAM位线
公开(公告)号：WO0127974A3
公开(公告)日：2001-10-18
申请号：PCT/EP0009739
申请日：2000-10-05
申请人： INFINEON TECHNOLOGIES AG , HOENIGSCHMID HEINZ , BRAUN GEORG
发明人： HOENIGSCHMID HEINZ , BRAUN GEORG
IPC分类号： G11C5/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10885 , G11C5/10 , H01L27/10811 , H01L27/10814
摘要： The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and being driven via word (3) and bit lines (14, 16). Said memory device is characterised in that the bit lines (14, 16) are led through two metallised sheets and in that the stacked capacitors (7, 8, 9) of the memory cells are located between these metallised sheets.
摘要翻译：根据本发明，提供了一种具有多个存储器单元的存储器装置的每一个包括至少一个选择晶体管和一个叠置电容器和经由字（3） - 和位线（14，16）是可控的。根据本发明的存储系统的特征在于：（14，16）在两个金属化被引导所述位线和所述层叠电容器（7，8，9）的金属化平面之间的存储器单元的布置。

8. 发明申请

WO0019443B1 CIRCUIT FOR GENERATING A REFERENCE VOLTAGE FOR READING OUT FROM A FERROELECTRIC MEMORY 审中-公开
标题翻译：为读取铁电存储器而产生参考电压的电路安排
公开(公告)号：WO0019443B1
公开(公告)日：2000-06-29
申请号：PCT/DE9902984
申请日：1999-09-17
申请人： SIEMENS AG , BRAUN GEORG , HOENIGSCHMID HEINZ , ROEHR THOMAS , KOWARIK OSKAR , HOFFMANN KURT
发明人： BRAUN GEORG , HOENIGSCHMID HEINZ , ROEHR THOMAS , KOWARIK OSKAR , HOFFMANN KURT
IPC分类号： G11C11/22 , G11C29/12
CPC分类号： G11C11/22
摘要： The invention relates to a circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with constant plate voltage (VP) from storage cells (C1, C2) of a ferroelectric memory via bit lines (B1, B2; BLt, bBLt). In the inventive circuit, a reference voltage device is comprised of two reference cells (DC1, DC0) which are subjected to the action of complementary signals. Said reference cells can be simultaneously read out from in order to generate the reference voltage in a selection and evaluation device (10).
摘要翻译：本发明涉及一种电路装置，用于读出并经由位线恒定板电压（VP）（B1，B2; BLT，BBLT）的强电介质存储器的存储器单元（C1，C2）的评价产生参考电压读出读出的信号，其中一个基准电压装置，其包括两者可以用信号互补参考细胞（DC1，DC0），其在同一时间，以产生在选择和评估装置（10），所述参考电压可以读出被采取行动。

9. 发明申请

WO0019443A2 CIRCUIT FOR GENERATING A REFERENCE VOLTAGE FOR READING OUT FROM A FERROELECTRIC MEMORY 审中-公开
公开(公告)号：WO0019443A2
公开(公告)日：2000-04-06
申请号：PCT/DE9902984
申请日：1999-09-17
申请人： SIEMENS AG , BRAUN GEORG , HOENIGSCHMID HEINZ , ROEHR THOMAS , KOWARIK OSKAR , HOFFMANN KURT
发明人： BRAUN GEORG , HOENIGSCHMID HEINZ , ROEHR THOMAS , KOWARIK OSKAR , HOFFMANN KURT
IPC分类号： G11C11/22 , G11C29/12
CPC分类号： G11C11/22
摘要： The invention relates to a circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with constant plate voltage (VP) from storage cells (C1, C2) of a ferroelectric memory via bit lines (B1, B2; BLt, bBLt). In the inventive circuit, a reference voltage device is comprised of two reference cells (DC1, DC0) which are subjected to the action of complementary signals. Said reference cells can be simultaneously read out from in order to generate the reference voltage in a selection and evaluation device (10).

10. 发明申请

WO03071554A2 FUSE CONCEPT AND METHOD OF OPERATION 审中-公开
标题翻译：保险丝的概念和操作方法
公开(公告)号：WO03071554A2
公开(公告)日：2003-08-28
申请号：PCT/EP0301630
申请日：2003-02-18
申请人： INFINEON TECHNOLOGIES AG
发明人： HOENIGSCHMID HEINZ , VIEHMANN HEINRICH
IPC分类号： G11C29/04 , G11C17/14 , G11C29/00 , G11C29/44
CPC分类号： G11C11/16 , G11C17/14 , G11C29/72 , G11C29/789
摘要： It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.
摘要翻译：难以制造半导体存储器件而没有任何错误的存储器存储单元。一个解决方案是生产比设备上所需的更多的存储单元，并且冗余存储单元被替换为故障存储单元。该解决方案要求将故障存储单元的地址与替换存储单元一起保存在存储器中。本发明教导了使用非易失性存储单元，特别是磁阻随机存取存储器（MRAM）单元来存储地址。非易失性存储单元可以有效地替代当前使用的激光熔丝，并且还在设备制造期间消除激光熔丝烧制步骤的优点。

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