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1. 发明申请

WO2004059728A2 METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING REDUCED STRESS AND SEMICONDUCTOR CHIP 审中-公开
标题翻译：制造具有降低应力和半导体芯片的集成电路的方法
公开(公告)号：WO2004059728A2
公开(公告)日：2004-07-15
申请号：PCT/EP0314415
申请日：2003-12-17
申请人： INFINEON TECHNOLOGIES AG
发明人： BRUCHHAUS RAINER , GERNHARDT STEFAN , HILLIGER ANDREAS , LIAN JINGYU , NAGEL NICOLAS , WELLHAUSEN UWE
IPC分类号： H01L21/8246 , H01L23/00 , H01L21/02 , H01L21/8239 , H01L27/105
CPC分类号： H01L27/11502 , H01L23/562 , H01L27/11507 , H01L27/1159 , H01L29/7842 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.
摘要翻译：为了减少弯曲，半导体芯片减小了对基板上的有效应力的应力。为了降低有效应力，在芯片的背面设置应力补偿层。应力补偿层产生与IC产生的应力相反的应力。因此，降低了基板上的整体或有效应力。

2. 发明申请

WO2004059739A3 MEMORY ARCHITECTURE WITH SERIES GROUPED MEMORY CELLS 审中-公开
标题翻译：存储器架构与系列分组存储器单元
公开(公告)号：WO2004059739A3
公开(公告)日：2004-09-30
申请号：PCT/EP0314637
申请日：2003-12-19
申请人： INFINEON TECHNOLOGIES AG
发明人： HILLIGER ANDREAS , BRUCHHAUS RAINER , WOHLFAHRT JOERG
IPC分类号： G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/10817 , H01L27/10852 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
摘要翻译：公开了具有串联结构的存储器阵列的IC。串联组的存储器单元包括并联耦合到电容器的晶体管。电容器包括第一和第二子电容器，一个堆叠在另一个的顶部。在堆叠中提供具有两个或更多个子电容器的电容器有利地增加电容器的电容而不增加表面积。

3. 发明申请

WO2004077541A2 A METHOD OF ETCHING FERROELECTRIC DEVICES 审中-公开
标题翻译：一种蚀刻电介质器件的方法
公开(公告)号：WO2004077541A2
公开(公告)日：2004-09-10
申请号：PCT/SG2004000034
申请日：2004-02-09
申请人： INFINEON TECHNOLOGIES AG , EGGER ULRICH , ZHUANG HAOREN , BRUCHHAUS RAINER
发明人： EGGER ULRICH , ZHUANG HAOREN , BRUCHHAUS RAINER
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/32139 , H01L21/31122 , H01L21/32136 , H01L28/55 , H01L28/60
摘要： A method of etching a ferroelectric device (100) having a ferroelectric layer (112) between a top and a bottom electrode (114, 108) is disclosed herein. Hardmasks (116, 118) are deposited on the top electrode (114), two or more hardmasks being spaced apart by narrow first regions (115) and spaced apart from other hardmasks by wider second regions (117). The top electrode (114) and ferroelectric layer (112) are then etched to pattern the top electrode (114) thus forming capacitors (102, 104), and the bottom electrode (108) is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode (108), but in the second regions the bottom electrode is severed. To pattern the bottom electrode (108), a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.
摘要翻译：本文公开了一种在顶部电极和底部电极（114,108）之间蚀刻具有铁电体层（112）的铁电体元件（100）的方法。硬掩模（116,118）沉积在顶部电极（114）上，两个或更多个硬掩模由窄的第一区域（115）间隔开，并且由较宽的第二区域（117）与其它硬掩模隔开。然后蚀刻顶部电极（114）和铁电体层（112）以对顶部电极（114）进行图案，从而形成电容器（102,104），并且通过其中第二区域蚀刻比第二区域更缓慢。那些在它们之间具有第一区域的电容器具有共同的底部电极（108），但是在第二区域中，底部电极被切断。为了对底部电极（108）进行图案化，其后采用基于CO的化学物质的氟基化学物质用于两步蚀刻工艺。

4. 发明申请

WO2004051743A2 RADIATION PROTECTION IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的辐射防护
公开(公告)号：WO2004051743A2
公开(公告)日：2004-06-17
申请号：PCT/EP0313411
申请日：2003-11-28
申请人： INFINEON TECHNOLOGIES AG , WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
发明人： WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
IPC分类号： G06F1/04 , H01L21/02 , H01L23/00 , H01L23/552 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/552 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.
摘要翻译：公开了降低对IC特征的辐射损伤。对辐射敏感的特征的至少一部分被辐射防护层覆盖。辐射防护层在例如IC的处理期间保护特征不被辐射损坏。在一个实施例中，辐射防护层包括贵金属，氧化物，合金或其化合物。

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