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    • 1. 发明申请
    • LOW PIN COUNT CONTROLLER
    • 低PIN计数控制器
    • WO2012140669A3
    • 2013-01-10
    • PCT/IN2012000253
    • 2012-04-09
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJIVOLETI SIVA RAGHURAMLOTTI RAJANITANDABOINA KRISHNA MOHAN
    • KANIGICHERLA BALAJIVOLETI SIVA RAGHURAMLOTTI RAJANITANDABOINA KRISHNA MOHAN
    • G06F13/36
    • G06F13/24G06F13/28G06F2213/0038
    • Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.
    • 这里描述的是具有多主机低引脚数(LPC)控制器(100)的系统,其被配置为便于多主机计算系统(110)的多个主机(115)共享公共外围设备。 在一个实现中,多主机LPC控制器(100)经由片上总线或LPC-IN芯片总线与主机(115)接口。 此外,多主机LPC控制器(100)包括LPC-IN控制器(160)和微控制器(155),用于在由主机(115)生成的请求中进行调节。 请求可以是目标访问,DMA访问和BM访问。 此外,多主机LPC控制器(100)被配置为以软件模式和自动模式操作。 基于多主机LPC控制器(100)正在操作的模式,由各种主机产生的请求被调节。
    • 2. 发明申请
    • USB VIRTUALIZATION
    • USB虚拟化
    • WO2012140668A2
    • 2012-10-18
    • PCT/IN2012000251
    • 2012-04-09
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJIVOLETI SIVA RAGHURAMDOMMETI SURYA NARAYANATANDABOINA KRISHNA MOHANLOTTI RAJANI
    • KANIGICHERLA BALAJIVOLETI SIVA RAGHURAMDOMMETI SURYA NARAYANATANDABOINA KRISHNA MOHANLOTTI RAJANI
    • G06F13/28G06F13/10Y02D10/14
    • Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.
    • 这里描述了用于虚拟化USB设备以使得能够在多处理器计算系统中的多个主机处理器之间共享USB设备的方法和系统。 用于共享USB设备的USB虚拟化单元包括每主机寄存器单元,每个主机寄存器单元对应于主处理器,包括主机寄存器接口,主机数据接口,配置寄存器和主机控制寄存器中的一个或多个,被配置为同时接收 来自用于USB设备的多个主机处理器中的一个或多个主机处理器的请求。 USB虚拟化单元还包括预取直接存储器访问(DMA),其被配置为预取与存储在缓冲器中的请求相关联的DMA描述符。 USB虚拟化单元还包括端点特定切换判定逻辑(ESL),其被配置为基于来自对应于每个请求的主处理器的本地存储器的DMA描述符调度数据访问。
    • 4. 发明申请
    • WIRELESS INTERFACE SHARING
    • 无线接口共享
    • WO2012143941A4
    • 2013-02-14
    • PCT/IN2012000271
    • 2012-04-17
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJIVOLETI SIVA RAGHURAMTANDABOINA KRISHNA MOHANKOPPARAPU SUMANBANDI SARVESHWARHALI KAPIL
    • KANIGICHERLA BALAJIVOLETI SIVA RAGHURAMTANDABOINA KRISHNA MOHANKOPPARAPU SUMANBANDI SARVESHWARHALI KAPIL
    • H04W92/10G06F9/445H04W88/06
    • H04W40/246H04L45/586H04W40/00
    • Described herein are methods and system for sharing a wireless interface (102) among various multiple host processors in a multi-processor computing system (100) to provide simultaneous access of a wireless network to the host processors. In one implementation the multi-host computing system (100), comprises a wireless interface (102) configured to connect to at least one of a plurality of wireless networks; and a wireless network access virtualization (WNAV) processor (108) communicatively coupled to the wireless interface (102), wherein the WNAV processor (108) is configured to multiplex data packets received from the plurality of hosts, transmit the multiplexed data packets to at least one of the plurality of wireless networks through the wireless interface (102), receive data packets from one of the plurality of wireless network through the wireless interface (102) and route the data packets to each of the plurality of hosts based on a media access control (MAC) address associated with each of the plurality of hosts.
    • 这里描述了用于在多处理器计算系统(100)中共享各种多个主机处理器之间的无线接口(102)的方法和系统,以提供无线网络同时访问主处理器。 在一个实现中,多主机计算系统(100)包括被配置为连接到多个无线网络中的至少一个的无线接口(102) 以及通信地耦合到所述无线接口(102)的无线网络接入虚拟化(WNAV)处理器(108),其中所述WNAV处理器(108)被配置为对从所述多个主机接收的数据分组进行复用,将所述复用的数据分组发送到 通过无线接口(102)的多个无线网络中的至少一个通过无线接口(102)从多个无线网络之一接收数据分组,并且基于媒体将数据分组路由到多个主机中的每一个 与所述多个主机中的每一个相关联的访问控制(MAC)地址。
    • 5. 发明申请
    • MULTI-HOST SATA CONTROLLER
    • 多主机SATA控制器
    • WO2012140670A3
    • 2013-01-10
    • PCT/IN2012000254
    • 2012-04-09
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJITANDABOINA KRISHNA MOHANVOLETI SIVA RAGHURAMYADAV KARAMVEER
    • KANIGICHERLA BALAJITANDABOINA KRISHNA MOHANVOLETI SIVA RAGHURAMYADAV KARAMVEER
    • G06F13/42
    • G06F3/0632G06F3/0625G06F3/067G06F13/126
    • Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.
    • 这里描述的是具有多主机SATA控制器(102)的系统,其被配置为提供两个或多个独立主机处理器(104)和单个SATA设备(108)之间的通信和控制。 在一个实现中,多主机SATA控制器(102)包括设备切换层(206),设备控制层(208),链路层(210)和物理层(212)。 设备切换层(206)允许主处理器(104)同时发布命令,而不是以顺序发布。 为此,设备切换层(206)具有对应于每个主处理器(104)的独立的主机设备寄存器(214)集合。 设备切换层(206)还具有独立的DMA引擎(216),以执行从相应主机系统存储器(105)预取的命令。 此外,命令切换引擎(220)可以在主机处理器(104)希望同时访问SATA设备(108)的情况下仲裁命令。
    • 9. 发明申请
    • MULTI-HOST SATA CONTROLLER
    • 多主机SATA控制器
    • WO2012140670A4
    • 2013-03-07
    • PCT/IN2012000254
    • 2012-04-09
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJITANDABOINA KRISHNA MOHANVOLETI SIVA RAGHURAMYADAV KARAMVEER
    • KANIGICHERLA BALAJITANDABOINA KRISHNA MOHANVOLETI SIVA RAGHURAMYADAV KARAMVEER
    • G06F13/42
    • G06F3/0632G06F3/0625G06F3/067G06F13/126
    • Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.
    • 这里描述的是具有多主机SATA控制器(102)的系统,该多主机SATA控制器被配置为提供两个或更多独立主处理器(104)和单个SATA设备(108)之间的通信和控制。 在一个实现中,多主机SATA控制器(102)包括设备交换层(206),设备控制层(208),链路层(210)和物理层(212)。 设备交换层(206)允许主处理器(104)同时而不是按顺序发布命令。 为此,设备交换层(206)具有对应于每个主处理器(104)的独立的一组主机设备寄存器(214)。 设备交换层(206)还具有独立的DMA引擎(216),以执行从各个主机系统存储器(105)预取命令。 此外,在两个主处理器(104)都希望同时访问SATA设备(108)的情况下,命令交换引擎(220)可以仲裁命令。
    • 10. 发明申请
    • WIRELESS INTERFACE SHARING
    • 无线接口共享
    • WO2012143941A3
    • 2013-01-17
    • PCT/IN2012000271
    • 2012-04-17
    • INEDA SYSTEMS PVT LTDKANIGICHERLA BALAJIVOLETI SIVA RAGHURAMTANDABOINA KRISHNA MOHANKOPPARAPU SUMANBANDI SARVESHWARHALI KAPIL
    • KANIGICHERLA BALAJIVOLETI SIVA RAGHURAMTANDABOINA KRISHNA MOHANKOPPARAPU SUMANBANDI SARVESHWARHALI KAPIL
    • H04W92/10G06F9/445H04W88/06
    • H04W40/246H04L45/586H04W40/00
    • Described herein are methods and system for sharing a wireless interface (102) among various multiple host processors in a multi-processor computing system (100) to provide simultaneous access of a wireless network to the host processors. In one implementation the multi-host computing system (100), comprises a wireless interface (102) configured to connect to at least one of a plurality of wireless networks; and a wireless network access virtualization (WNAV) processor (108) communicatively coupled to the wireless interface (102), wherein the WNAV processor (108) is configured to multiplex data packets received from the plurality of hosts, transmit the multiplexed data packets to at least one of the plurality of wireless networks through the wireless interface (102), receive data packets from one of the plurality of wireless network through the wireless interface (102) and route the data packets to each of the plurality of hosts based on a media access control (MAC) address associated with each of the plurality of hosts.
    • 这里描述的是用于在多处理器计算系统(100)中的各种多主处理器之间共享无线接口(102)以提供无线网络同时访问主处理器的方法和系统。 在一个实施方式中,多主计算系统(100)包括被配置为连接到多个无线网络中的至少一个的无线接口(102) 以及通信地耦合到所述无线接口(102)的无线网络访问虚拟化(WNAV)处理器(108),其中所述WNAV处理器(108)被配置为对从所述多个主机接收的数据分组进行多路复用,将所述多路复用数据分组传输到 通过无线接口(102)的多个无线网络中的至少一个无线网络,通过无线接口(102)从多个无线网络中的一个接收数据分组,并且基于媒体将数据分组路由到多个主机中的每一个 访问控制(MAC)地址与多个主机中的每一个相关联。