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1. 发明申请

WO2009140052A3 METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR 审中-公开
标题翻译：金属栅组合结构和方法，包括金属保险丝，抗保险丝和/或电阻
公开(公告)号：WO2009140052A3
公开(公告)日：2010-01-21
申请号：PCT/US2009041861
申请日：2009-04-28
申请人： IBM , ESHUN EBENEZER E , HE ZHONG-XIANG , RASSEL ROBERT M , COOLBAUGH DOUGLAS , GEBRESELASIE EPHREM G , WANG PING-CHUAN , KIM DEOK-KEE , KOTHANDARAMAN CHANDRASEKHARAN , ROBSON NORMAN W , MOY DAN , SAFRAN JOHN M , STEIN KENNETH J , HO HERBERT L , YAN HONGWEN
发明人： ESHUN EBENEZER E , HE ZHONG-XIANG , RASSEL ROBERT M , COOLBAUGH DOUGLAS , GEBRESELASIE EPHREM G , WANG PING-CHUAN , KIM DEOK-KEE , KOTHANDARAMAN CHANDRASEKHARAN , ROBSON NORMAN W , MOY DAN , SAFRAN JOHN M , STEIN KENNETH J , HO HERBERT L , YAN HONGWEN
IPC分类号： H01L21/335
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

2. 发明申请

WO02058117A3 METAL-INSULATOR-METAL CAPACITOR IN COPPER 审中-公开
标题翻译：金属绝缘子 - 金属电容器在铜
公开(公告)号：WO02058117A3
公开(公告)日：2003-08-28
申请号：PCT/EP0201049
申请日：2002-01-16
申请人： IBM , INFINEON TECHNOLOGIES CORP , IBM FRANCE
发明人： ARMACOST MICHAEL D , AUGUSTIN ANDREAS K , FRIESE GERALD R , HEIDENREICH JOHN E III , HUECKEL GARY R , STEIN KENNETH J
IPC分类号： H01L27/04 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/822 , H01L23/522
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136 , H01L21/76802 , H01L21/76816 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mu ) with a bottom etch stop layer (104), a composite bottom plate (110) having an aluminium layer below a TiN layer, an oxide capacitor dielectric (120), and a top plate (130) of TiN. The process involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.
摘要翻译：在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以内）的区域，底部蚀刻停止层（104），在TiN层下方具有铝层的复合底板（110），氧化物电容器电介质（120）和TiN的顶板（130）。该方法包括蚀刻顶板以留下电容器区域，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质并完成氮化物盖层的穿透。

3. 发明申请

WO2004038916A3 MICRO-ELECTROMECHANICAL VARACTOR WITH ENHANCED TUNING RANGE 审中-公开
标题翻译：具有增强调谐范围的微电子变压器
公开(公告)号：WO2004038916A3
公开(公告)日：2004-08-12
申请号：PCT/EP0312399
申请日：2003-09-18
申请人： IBM , IBM FRANCE
发明人： CHINTHAKINDI ANIL K , GROVES ROBERT A , STEIN KENNETH J , SUBBANNA SESHADRI , VOLANT RICHARD P
IPC分类号： B81B7/00 , B81C1/00 , H01G5/011 , H01G5/18 , H03J3/18 , B81B3/00 , H01G5/16
CPC分类号： H01G5/18 , B81B2201/01 , H01G5/011 , Y10S257/924
摘要： A three-dimensional micro-electromechanical (MEM) varactor is described wherein a movable beam (50) and fixed electrodes (51) are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.
摘要翻译：描述了三维微机电（MEM）变容二极管，其中可移动光束（50）和固定电极（51）分别制造在彼此耦合的分离的基板上。具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。由于所涉及的驱动力恒定，可以获得大的电容调谐范围。该装置的三维方面具有较大的表面积。当提供大的纵横比特征时，可以使用较低的致动电压。在制造时，MEMS器件被完全封装，不需要额外的器件封装。此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

4. 发明申请

WO03001584A8 A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：非自对准信号异相双极晶体管
公开(公告)号：WO03001584A8
公开(公告)日：2004-05-27
申请号：PCT/US0219789
申请日：2002-06-19
申请人： IBM
发明人： JAGANNATHAN BASANTH , JENG SHWU-JEN , JOHNSON JEFFREY B , JOHNSON ROBB A , LANZEROTTI LOUIS D , STEIN KENNETH J , SUBBANNA SESHADRI
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/737 , H01L31/11
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.
摘要翻译：一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口叠加。这通过使发射器基座（66）比发射器开口更宽来实现。这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

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