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    • 2. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE
    • 薄膜晶体管阵列面板和导电结构
    • WO2017121211A1
    • 2017-07-20
    • PCT/CN2016/108892
    • 2016-12-07
    • HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.HON HAI PRECISION INDUSTRY CO., LTD.
    • KAO, YichunLIN, XinyeSHIH, PoliCHANG, WeichihLU, YimingWU, Iwei
    • H01L29/12H01L21/77
    • H01L29/66969H01L21/441H01L21/47635H01L21/477H01L27/124H01L29/24H01L29/41733H01L29/45H01L29/458H01L29/66765H01L29/78669H01L29/78678H01L29/7869
    • A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3). The content ratio differentiation between the first and the third sub-layers (105-1, 105-3) affects a lateral etch profile associated with a gap (106) generated in the second conductive layer (105) between the source and the drain electrodes (105a, 105b), where the associated gap (106) width in the third sub-layer (105-3) is wider than that in the first sub-layer (105-1).
    • 薄膜晶体管阵列面板包括:第一导电层(102),其包括栅电极; 布置在所述栅极上方的沟道层(104) 和设置在沟道层(104)上的第二导电层(105)。 第二导电层(105)包括限定源电极(105a)和漏电极(105b)的多层部分,其包括第一子层(105-1),第二子层(105-2) )和第三子层(105-3),其顺序地一个在另一个之上。 第三和第一子层(105-3,105-1)都包括铟和氧化锌材料。 第一子层(105-1)中的铟与锌的含量比大于第三子层(105-3)中的铟与锌的含量之比。 第一和第三子层(105-1,105-3)之间的含量比例区分影响与源极和漏极之间的第二导电层(105)中产生的间隙(106)相关的横向蚀刻轮廓 (105a,105b),其中第三子层(105-3)中的相关间隙(106)宽度比第一子层(105-1)中的宽度更宽。
    • 4. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列面板
    • WO2017121216A1
    • 2017-07-20
    • PCT/CN2016/109348
    • 2016-12-10
    • HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.HON HAI PRECISION INDUSTRY CO., LTD.
    • KAO, YichunLIN, HsinhuaSHIH, PoliCHANG, WeichihLU, IminWU, Iwei
    • G02F1/1362H01L29/786
    • G02F1/1368H01L29/786
    • A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    • 半导体器件包括设置在衬底(101)上方并限定复合横向蚀刻轮廓的多层结构。 多层结构包括设置在衬底(101)上方的下部子层(105-1),并且包括包含铟和锌的金属氧化物材料,下部子层(105-1)中的铟和锌含量 )基本上限定第一铟与锌的含量比率; 设置在所述下子层(105-1)上并包含金属材料的中间子层(105-2) 设置在所述中间子层(105-2)上并且包括金属氧化物材料的上子层(105-3),所述金属氧化物材料包括铟和锌,所述上子层(105-3)中的铟至锌含量, 基本上限定小于所述第一铟与锌含量比的第二铟与锌含量比; 以及形成在横向刻蚀表面上的横向副产物层,基本上包括中间子层(105-2)中的金属材料的金属氧化物。