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1. 发明申请

WO2008103860A1 APPARATUS FOR MEASURING IQ IMBALANCE 审中-公开
标题翻译：测量智商不平等的方法
公开(公告)号：WO2008103860A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/054629
申请日：2008-02-21
申请人： GCT SEMICONDUCTOR, INC. , LEE, Kyeongho , PARK, Joonbae , LEE, Jeong-woo , LEE, Seung-wook , LEE, Eal Wan
发明人： LEE, Kyeongho , PARK, Joonbae , LEE, Jeong-woo , LEE, Seung-wook , LEE, Eal Wan
IPC分类号： H04J15/00 , H04J11/00 , H04B7/04 , H04B7/08
CPC分类号： H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： The present invention relates to an apparatus and a method for measuring an IQ imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.
摘要翻译：本发明涉及一种用于测量IQ不平衡的装置和方法。根据本发明总体构思的一个实施例可以提供一种用于测量在IQ上变频混频器中产生的Tx IQ不平衡和在IQ下变频混频器中产生的Rx IQ不平衡的方法，其包括测量对应于 Rx IQ不平衡与Tx IQ不平衡的第一组合，测量对应于Rx IQ不平衡与Tx IQ不平衡的第二组合的第二IQ不平衡，并从第一IQ获得Tx IQ不平衡和Rx IQ不平衡不平衡和第二智商失衡。

2. 发明申请

WO2005022933A2 SYSTEM AND METHOD FOR FILTERING SIGNALS IN A TRANSCEIVER 审中-公开
标题翻译：用于在收发器中过滤信号的系统和方法
公开(公告)号：WO2005022933A2
公开(公告)日：2005-03-10
申请号：PCT/US2004/027799
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR, INC. , JEON, Young-Deuk , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
发明人： JEON, Young-Deuk , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04Q
CPC分类号： H04B1/1027 , H03H11/1252 , H03H11/1291 , H03J1/0008 , H04B1/44
摘要： A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals. The system and method are particularly well suited to controlling the filtering of signals at the front-end of the transceiver having a direct-conversion architecture and in general ones performing time-multiplexing applications.
摘要翻译：用于对通信系统中的信号进行滤波的系统和方法通过沿收发器的发射机和接收机路径选择性地连接滤波器来降低硬件和芯片尺寸的要求。在操作中，当收发器处于发射机模式时，控制器产生用于沿着发射机路径连接滤波器的信号，并且当发射机处于接收机模式时，控制器沿着接收机路径连接滤波器。然后，控制器产生附加信号，用于基于连接的路径设置滤波器的一个或多个参数，或者基于收发器的操作模式进行不同的设置。在一个变型中，控制器设置耦合到滤波器的附加元件的参数作为进一步控制发射机和接收机信号的处理的一种方式。该系统和方法特别适用于控制在具有直接转换架构的收发器的前端处的信号的滤波，并且通常执行时间复用应用。

3. 发明申请

WO2004012350A1 AN RF FRONT END WITH REDUCED CARRIER LEAKAGE 审中-公开
标题翻译：一个RF前端，减少载波泄漏
公开(公告)号：WO2004012350A1
公开(公告)日：2004-02-05
申请号：PCT/US2003/023366
申请日：2003-07-28
申请人： GCT SEMICONDUCTOR, INC. , SONG, Eunseok , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
发明人： SONG, Eunseok , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04B1/00
CPC分类号： H04B1/28 , H04B1/525
摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider (407) that divides an input signal frequency by a predetermined value to produce an output signal frequency (417); and a frequency mixer (405, 406) that mixes the output signal frequency (417) with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency (417) and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency (417). The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.
摘要翻译：公开了一种在射频前端提供频率转换的方法和装置，包括将输入信号频率除以预定值以产生输出信号频率的分频器（407）; 以及混频器（405,406），其将所述输出信号频率（417）与载波信号频率混频以产生转换的信号频率，其基本上等于所述输出信号频率（417）和所述载波信号频率。选择预定值和输入信号频率使得载波信号频率基本上不等于输出信号频率的整数倍（417）。该方法和装置可用于包括无线通信系统和无线LAN系统的无线通信接收机。

4. 发明申请

WO2008098155A1 APPARATUS FOR MEASURING IQ IMBALANCE 审中-公开
标题翻译：测量智商不平等的方法
公开(公告)号：WO2008098155A1
公开(公告)日：2008-08-14
申请号：PCT/US2008/053385
申请日：2008-02-08
申请人： GCT SEMICONDUCTOR, INC. , LEE, Kyeongho , PARK, Joonbae , LEE, Jeong-Woo , LEE, Seung-Wook , LEE, Eal, Wan
发明人： LEE, Kyeongho , PARK, Joonbae , LEE, Jeong-Woo , LEE, Seung-Wook , LEE, Eal, Wan
IPC分类号： H04B17/02 , H03H7/30
CPC分类号： H03D3/009
摘要： The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.
摘要翻译：本发明总体构思涉及用于测量IQ不平衡的装置和/或方法。在一个实施例中，检测器可以通过IQ不平衡来使用包括期望信号和对应图像信号的第一IQ信号来测量由IQ不平衡引起的误差。检测器可以包括解旋器，以将第一IQ信号扭曲第一角度频率以获得第二IQ信号并且将第一IQ信号解除第二角度频率以获得第三IQ信号，DC估计器以获得第四IQ信号对应于第二IQ信号的DC分量和对应于第三IQ信号的DC分量的第五IQ信号，并且控制器可以从第四IQ信号和第五IQ信号确定增益误差或相位误差。

5. 发明申请

WO2006055821A2 AN INTEGRATED WIRELESS RECEIVER AND A WIRELESS RECEIVING METHOD THEREOF 审中-公开
标题翻译：一种集成的无线接收器及其无线接收方法
公开(公告)号：WO2006055821A2
公开(公告)日：2006-05-26
申请号：PCT/US2005/041922
申请日：2005-11-18
申请人： GCT SEMICONDUCTOR, INC. , PARK, Joonbae , LEE, Seung-wook , LEE, Jeong-woo , LEE, Kyeongho
发明人： PARK, Joonbae , LEE, Seung-wook , LEE, Jeong-woo , LEE, Kyeongho
IPC分类号： H04B1/28
CPC分类号： H04B1/26
摘要： A wireless receiver and a wireless receiving method are provided wherein a frequency of a radio frequency (RF) is down-converted into a frequency of a substantially zero intermediate frequency (IF) signal or a substantially low IF signal. The down-converted signal may be filtered by an integrated filter having a low quality factor and then up-converted again into a particular IF signal, thereby integrating an external element. For example, a receiving device may receive a RF signal in a required band. A frequency down-converting device may down-convert a frequency so that a center frequency of the RF signal becomes zero. A channel select filtering device may select a required channel from the signals whose frequency is down-converted. An IF signal converting device may up-convert a frequency of the channel selected signal into a required IF. An IF processing device may extract a baseband signal after the converted IF signal is inputted and processed. An amplifying device may amplify a signal with a gain required in a process of converting a frequency.
摘要翻译：提供了一种无线接收机和无线接收方法，其中射频（RF）的频率被下变频为基本为零的中频（IF）信号的频率或基本上低的IF 信号。下变频后的信号可以通过具有低品质因数的集成滤波器进行滤波，然后再次上变频为特定IF信号，从而对外部元件进行整合。例如，接收设备可以接收所需带中的RF信号。降频转换设备可以对频率进行降频转换，使得RF信号的中心频率变为零。信道选择滤波设备可以从频率被下变频的信号中选择所需的信道。 IF信号转换装置可以将频道选择信号的频率上变频为所需的IF。 IF处理设备可以在转换的IF信号被输入和处理之后提取基带信号。放大设备可以放大具有在转换频率的过程中所需的增益的信号。

6. 发明申请

WO2006036749A2 APPARATUS AND METHOD OF OSCILLATING WIDEBAND FREQUENCY 审中-公开
标题翻译：振荡频率的装置和方法
公开(公告)号：WO2006036749A2
公开(公告)日：2006-04-06
申请号：PCT/US2005/034021
申请日：2005-09-21
申请人： GCT SEMICONDUCTOR, INC. , PARK, Joonbae , LEE, Seung-Wook , LEE, Jeong-Woo , LEE, Kyeongho
发明人： PARK, Joonbae , LEE, Seung-Wook , LEE, Jeong-Woo , LEE, Kyeongho
IPC分类号： H01P5/12
CPC分类号： H03L7/113 , H03L7/087 , H03L7/10 , H03L7/187
摘要： An apparatus and method of oscillating a wideband frequency are disclosed. The apparatus includes: a frequency oscillating unit for oscillating a predetermined frequency; a phase-locked loop for comparing the oscillated frequency and a reference frequency by feedbacking the oscillated frequency from the frequency oscillating unit and fixing an oscillating frequency of the frequency oscillating unit; and a variable dividing unit for varying a division ratio to approach to a frequency band required by the oscillating frequency and dividing the oscillating frequency.
摘要翻译：公开了一种振荡宽带频率的装置和方法。该装置包括：用于振荡预定频率的频率振荡单元; 用于通过反馈来自频率振荡单元的振荡频率并固定频率振荡单元的振荡频率来比较振荡频率和参考频率的锁相环; 以及可变分割单元，用于改变分频比以接近振荡频率所需的频带并分频振荡频率。

7. 发明申请

WO2008127268A2 RADIO FREQUENCY INTEGRATED CIRCUIT 审中-公开
标题翻译：无线电频率综合电路
公开(公告)号：WO2008127268A2
公开(公告)日：2008-10-23
申请号：PCT/US2007/017865
申请日：2007-08-13
申请人： GCT SEMICONDUCTOR, INC. , PARK, Joonbae , LEE, Kyeongho , KOO, Yido , LEE, Jeong, Woo
发明人： PARK, Joonbae , LEE, Kyeongho , KOO, Yido , LEE, Jeong, Woo
IPC分类号： H04Q7/22
CPC分类号： H04B1/1607
摘要： Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.
摘要翻译： RFIC的实施例和用于相同和移动终端的方法可以在内部减小输入电压以向射频收发器提供规定的电压。 RFIC的实施例可以具有高效率和/或低噪声。在一个实施例中，设备可以包括PMIC和RFIC。 RFIC可以包括用于执行RF传输和RF接收的RF收发器，用于降低由PMIC提供的电压的DC-DC转换器和LDO调节器，以将降低的电压调节到由RF收发器使用的固定电压。

8. 发明申请

WO2008036389A3 FREQUENCY SYNTHESIZER USING TWO PHASE LOCKED LOOPS 审中-公开
公开(公告)号：WO2008036389A3
公开(公告)日：2008-03-27
申请号：PCT/US2007/020450
申请日：2007-09-21
申请人： GCT SEMICONDUCTOR, INC. , PARK, Joonbae , LEE, Kyeongho , KOO, Yido , LEE, Jeong-woo
发明人： PARK, Joonbae , LEE, Kyeongho , KOO, Yido , LEE, Jeong-woo
IPC分类号： H04B1/06 , H04B7/00
摘要： The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and die second output frequency.

9. 发明申请

WO2005022597A2 INTEGRATED CIRCUIT PACKAGE HAVING AN INDUCTANCE LOOP FORMED FROM A MULTI-LOOP CONFIGURATION 审中-公开
标题翻译：具有从多环配置形成的电感环的集成电路封装
公开(公告)号：WO2005022597A2
公开(公告)日：2005-03-10
申请号：PCT/US2004/027797
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR, INC. , KOO, Yido , HUH, Hyungki , LEE, Kang, Yoon , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
发明人： KOO, Yido , HUH, Hyungki , LEE, Kang, Yoon , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H01L
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01043 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
摘要翻译：集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线到包的第二个I / O引脚。为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

10. 发明申请

WO2005022599A2 INTEGRATED CIRCUIT PACKAGE HAVING INDUCTANCE LOOP FORMED FROM SAME-PIN-TO-SAME-BONDING-PAD STRUCTURE 审中-公开
标题翻译：集成电路封装具有形成于同一针一致结合垫结构的电感环
公开(公告)号：WO2005022599A2
公开(公告)日：2005-03-10
申请号：PCT/US2004/027855
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR, INC. , KOO, Yido , HUH, Hyungki , LEE, Kang, Yoon , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
发明人： KOO, Yido , HUH, Hyungki , LEE, Kang, Yoon , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H01L
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.
摘要翻译：集成电路封装包括由连接键合线和一个或多个输入/输出（I / O）封装引脚形成的电感回路。在一个实施例中，电感回路由将集成电路芯片上的键合焊盘连接至封装的I / O引脚的第一导线和将相同键合焊盘连接至相同引脚的第二导线形成。通过在集成电路封装的极限内形成电感回路，实现了对空间要求的实质性减少，这反过来又促进了小型化。

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