专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010076667A1 CLOCK GLITCH DETECTION CIRCUIT 审中-公开
标题翻译：时钟检测电路
公开(公告)号：WO2010076667A1
公开(公告)日：2010-07-08
申请号：PCT/IB2009/050011
申请日：2009-01-05
申请人： FREESCALE SEMICONDUCTOR, INC. , ROHLEDER, Michael , KOCH, Thomas , LITOVTCHENKO, Vladimir , LUEDEKE, Thomas
发明人： ROHLEDER, Michael , KOCH, Thomas , LITOVTCHENKO, Vladimir , LUEDEKE, Thomas
IPC分类号： H03K5/00
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit (402) for detecting clock glitches in a clock signal (400), a master counter (412) is clocked by the clock signal and memorizes a master count N M . An incrementer (428) advances the master count by one increment. A slave counter (420) is clocked by the clock signal and memorizes a slave count N S . The slave count is retarded relative to the master count by at least P clock edges. A comparator (434) determines whether the difference N M - N S between the master count and the slave count is at least P. In a related aspect, a synchronous circuit (708) comprises a clock tree (790, 792, 793, 794, 795) for transmitting a clock signal (700) from a start point (790) to one or more other points, the start point and the other points comprising a first point (792) and second point (793). A first counter (712) is clocked by the clock signal at the first point (792) and memorizes a first count N 1 . A first incrementer (728) advances the first count N 1 by one increment. A second counter (713) is clocked by the clock signal at the second point (793) and memorizes a second count N 2 . A second incrementer (729) advances the second count N 2 by one increment. A comparator (782) determines the difference N 1 - N 2 between the first count N 1 and the second count N 2 , or determines whether the first count N 1 and the second count N 2 differ. The synchronous circuit (708) may comprise the first circuit (402). A second circuit (504) for detecting clock glitches in a clock signal (500) is also provided. The second circuit (504) is intended to be integrated in the synchronous circuit (708).
摘要翻译：在用于检测时钟信号（400）中的时钟毛刺的第一电路（402）中，主计数器（412）由时钟信号计时，并存储主计数NM。增量器（428）将主计数递增一个增量。从计数器（420）由时钟信号计时，并存储从计数NS。从机计数相对于主计数延迟至少P个时钟沿。比较器（434）确定主计数和从计数之间的差值NM-NS是否至少为P。在相关方面，同步电路（708）包括时钟树（790,792,793,794,795 ），用于将起始点（790）的时钟信号（700）发送到一个或多个其他点，所述起始点和包括第一点（792）和第二点（793）的其他点。第一计数器（712）由第一点（792）处的时钟信号计时，并存储第一计数器N1。第一增量器（728）使第一计数N1前进一个增量。第二计数器（713）由第二点（793）处的时钟信号计时，并存储第二计数N2。第二增量器（729）使第二计数N2前进一个增量。比较器（782）确定第一计数N1和第二计数N2之间的差N1-N2，或者确定第一计数N1和第二计数N2是否不同。同步电路（708）可以包括第一电路（402）。还提供了用于检测时钟信号（500）中的时钟毛刺的第二电路（504）。第二电路（504）旨在集成在同步电路（708）中。

2. 发明申请

WO2008096208A1 REQUEST CONTROLLER, PROCESSING UNIT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：要求控制器，处理单元，控制要求和计算机程序产品的方法
公开(公告)号：WO2008096208A1
公开(公告)日：2008-08-14
申请号：PCT/IB2007/050420
申请日：2007-02-08
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , LITOVTCHENKO, Vladimir
发明人： BOGENBERGER, Florian , LITOVTCHENKO, Vladimir
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit . The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value . The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.
摘要翻译：一种请求控制器，用于控制一个或多个半导体数据处理单元的请求处理。资源控制器包括控制器输入，用于接收处理单元的切换以切换处理单元的上下文或者将处理单元从当前操作切换到另一操作的请求。资源控制器包括其中可以存储一个或多个预算值的资源预算存储器。预算值表示处理单元的资源量。资源控制器还具有预算控制器，其包括连接到请求控制器输入的第一预算控制器输入。第二个预算控制器输入连接到存储器。比较器连接到第一预算控制器输入和第二控制器输入，用于将与请求相关联的消耗值与预算值进行比较。比较器包括比较器输出，用于当比较满足预定的准许标准时输出请求授权信号，并且当比较满足预定的拒绝标准时输出请求拒绝值。数据控制器连接到资源预算存储器和比较器输出端，用于在输出请求授权信号时调整预算值。

3. 发明申请

WO2008099238A1 REQUEST CONTROLLER, PROCESSING UNIT, ARRANGEMENT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：请求控制器，处理单元，安排，控制请求和计算机程序产品的方法
公开(公告)号：WO2008099238A1
公开(公告)日：2008-08-21
申请号：PCT/IB2007/050511
申请日：2007-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
发明人： LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
IPC分类号： G06F13/24 , G06F9/48
CPC分类号： G06F13/24 , G06F9/4812
摘要： A request controller (2) for controlling requests of a processing unit. The request controller may include an request controller input (200-206) for receiving a request and a request processing unit (22) connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current operation to another operation. The request processing unit may decide on the request based on a decision criterion. A request controller output (21 ) may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit (222) including: a state input (2221 ) for receiving information about a current state of a system including the processing unit; and a request input (2220) for receiving information about a received request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit (222) may further include a control logic output (2222) for outputting a request grant signal when the request is granted.
摘要翻译：一种用于控制处理单元的请求的请求控制器（2）。请求控制器可以包括用于接收请求的请求控制器输入（200-206）和连接到请求控制器输入的请求处理单元（22）。请求可以请求切换所述处理单元的上下文或者将处理单元从当前操作切换到另一操作。请求处理单元可以基于判定标准来决定请求。请求控制器输出（21）可以连接到请求处理单元，用于输出关于至少授权请求的信息。所述请求处理单元可以包括：控制逻辑单元（222），包括：状态输入（2221），用于接收关于包括所述处理单元的系统的当前状态的信息; 以及用于接收关于接收到的请求的信息的请求输入（2220）。控制逻辑单元可以被布置为确定接收到的请求是否属于处理器的当前状态，以便当接收到的请求属于当前状态时授予该请求，并且在请求不属于该状态的情况下拒绝该请求当前状态。控制逻辑单元（222）还可以包括用于当请求被授权时输出请求授权信号的控制逻辑输出（2222）。

4. 发明申请

WO2007147441A1 METHOD AND SYSTEM OF GROUPING INTERRUPTS FROM A TIME-DEPENDENT DATA STORAGE MEANS 审中-公开
标题翻译：从时间依赖数据存储方式分组中断的方法和系统
公开(公告)号：WO2007147441A1
公开(公告)日：2007-12-27
申请号：PCT/EP2006/063473
申请日：2006-06-22
申请人： FREESCALE SEMICONDUCTOR, INC. , PATZELT, Christoph , LITOVTCHENKO, Vladimir , MOELLER, Dirk
发明人： PATZELT, Christoph , LITOVTCHENKO, Vladimir , MOELLER, Dirk
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of: providing each part of the data storage means with an indicator of an event associated with the part; generating interrupts upon the occurrence of events in different parts of the data storage means; allocating interrupts associated with substantially the same part of the data storage means to a same processing means.
摘要翻译：根据中断的类型对来自时间相关数据存储装置的中断进行分组的方法，所述方法包括以下步骤：向数据存储装置的每个部分提供与该部分相关联的事件的指示符; 在数据存储装置的不同部分发生事件时产生中断; 将与数据存储装置的基本相同的部分相关联的中断分配给相同的处理装置。

5. 发明申请

WO2007128347A1 DATA COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR BUFFERING DATA 审中-公开
标题翻译：数据通信单元，集成电路和缓冲数据的方法
公开(公告)号：WO2007128347A1
公开(公告)日：2007-11-15
申请号：PCT/EP2006/062164
申请日：2006-05-09
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , MOELLER, Dirk , PATZELT, Christoph
发明人： LITOVTCHENKO, Vladimir , MOELLER, Dirk , PATZELT, Christoph
IPC分类号： G06F13/38 , G06F9/46 , H04L12/40 , G06F5/12
CPC分类号： G06F5/12 , G06F9/52 , G06F9/526 , G06F2205/123
摘要： A data communication unit (500) comprises a host processor (505) operably coupled to a communication controller (515) having a plurality of buffers (520, 525) comprising a plurality of data elements. The plurality of data elements comprise a lock data element (535) for access by the host processor (505) to acquire sole use of a respective buffer of the plurality of buffers (520, 525) and a commit data element (530) for access by the host processor (505) once sole use of the respective buffer has been acquired wherein use of the lock data element (535) enables the host processor (505) to uncommit a transmit buffer that has previously been committed for transmission by the communication controller (515).
摘要翻译：数据通信单元（500）包括可操作地耦合到具有包括多个数据元素的多个缓冲器（520,525）的通信控制器（515）的主机处理器（505）。多个数据元素包括锁数据元素（535），用于由主机处理器（505）进行访问以获取对多个缓冲器（520,525）的相应缓冲器的唯一使用以及用于访问的提交数据元素（530）由主机处理器（505）一旦获得了相应缓冲器的唯一使用，其中使用锁定数据元素（535）使得主机处理器（505）能够使先前已被提交以供通信控制器发送的发送缓冲器（515）。

6. 发明申请

WO2015040454A1 ELECTRONIC DEVICE HAVING MULTIPLEXED INPUT/OUTPUT TERMINALS 审中-公开
标题翻译：具有多路输入/输出端子的电子设备
公开(公告)号：WO2015040454A1
公开(公告)日：2015-03-26
申请号：PCT/IB2013/058638
申请日：2013-09-18
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , KRUECKEN, Josef Maria Joachim
发明人： LITOVTCHENKO, Vladimir , KRUECKEN, Josef Maria Joachim
IPC分类号： H03K19/0175 , H03K19/173
CPC分类号： G06F11/3051 , G01R31/31723 , G06F11/2221 , G06F11/3041 , H03K5/04 , H03K19/1737
摘要： An electronic device (200) has terminals (202) for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver (203) and a terminal control circuit (212) for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker (204,204') arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error.
摘要翻译：电子设备（200）具有用于将内部信号与其他电子设备接口的终端（202）。每个端子电耦合到终端驱动器（203）和终端控制电路（212），用于接收定义终端的属性和复用的终端配置。根据终端配置设置终端驱动程序的实际配置。所述设备具有至少一个终端检查器（204,204'），用于将实际配置与至少一个检查配置进行比较，所述检查配置定义终端驱动器的配置，所述配置被允许或不被允许，并且当所述比较指示一个不允许的配置，将实际配置设置为默认配置。通过监视多路复用终端的配置，并且在错误时切换到默认配置，可以实现系统中设备的安全操作。

7. 发明申请

WO2014125326A1 CONFIGURATION CONTROLLER FOR AND A METHOD OF CONTROLLING A CONFIGURATION OF A CIRCUITRY 审中-公开
标题翻译：配置控制器和控制电路配置的方法
公开(公告)号：WO2014125326A1
公开(公告)日：2014-08-21
申请号：PCT/IB2013/051140
申请日：2013-02-12
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir
发明人： LITOVTCHENKO, Vladimir
IPC分类号： G06F13/14 , G06F13/16
CPC分类号： G06F9/44505 , G06F13/14 , G06F13/16 , G06F13/1694
摘要： A configuration controller CC, (100) for and a method of controlling a configuration of a circuitry DEV, (122) are provided. The configuration controller CC, (100) comprises an input (108), a selection checker CHK, (102), a data selector DS, (118) and an output (114). The input (108) receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker CHK, (102) checks a correctness of the received input configuration selection signal and provides to the data selector DS, (118) a selection signal (112) which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector DS, (118) selects configuration data from its internal configuration data storage (116) in accordance with the selection signal (112) and provides the selected configuration data to the output (114).
摘要翻译：提供了用于控制电路DEV，（122）的配置的配置控制器CC（100）和控制电路DEV的配置的方法。配置控制器CC，（100）包括输入（108），选择检查器CHK，（102），数据选择器DS，（118）和输出（114）。输入（108）接收根据特定编码方案编码的输入配置选择信号。选择检查器CHK（102）检查接收到的输入配置选择信号的正确性，并向数据选择器DS提供（118）选择信号（112），其指示如果输入配置选择数据正确则指定特定配置选择，如果输入配置选择信号根据特定编码方案不正确，则表示默认配置选择。数据选择器DS（118）根据选择信号（112）从其内部配置数据存储器（116）中选择配置数据，并将选择的配置数据提供给输出端（114）。

8. 发明申请

WO2013076529A1 SYSTEM-ON-CHIP, METHOD OF MANUFACTURE THEREOF AND METHOD OF CONTROLLING A SYSTEM-ON-CHIP 审中-公开
标题翻译：系统芯片，其制造方法和控制系统芯片的方法
公开(公告)号：WO2013076529A1
公开(公告)日：2013-05-30
申请号：PCT/IB2011/055253
申请日：2011-11-23
申请人： FREESCALE SEMICONDUCTOR, INC. , REGNER, Markus , LITOVTCHENKO, Vladimir , LUEPKEN, Harald
发明人： REGNER, Markus , LITOVTCHENKO, Vladimir , LUEPKEN, Harald
IPC分类号： G06F13/14 , G06F11/00 , G06F1/00
CPC分类号： G06F9/44505 , G06F1/12 , G06F13/14 , G06F15/80 , G06F17/505
摘要： A system-on-chip comprises a plurality of functional domains (106, 108, 110). The plurality of functional domains (106, 108, 110) comprise a first domain (106) and a second domain (108), the first domain (106) having a first active mode of operation and the second domain (108) having a second active mode of operation different from the first active mode of operation. The system-on-chip also comprises a control unit operably coupled to the first and second domains and capable of placing the first domain in the first active mode and the second domain in the second active mode so that the first domain (106) is in the first active mode and the second domain (108) is in the second active mode substantially contemporaneously. The first active mode of operation is functionally different from the second active mode of operation.
摘要翻译：片上系统包括多个功能域（106,108,110）。多个功能域（106,108,110）包括第一域（106）和第二域（108），第一域（106）具有第一主动操作模式，第二域（108）具有第二域主动运行模式与第一主动运行模式不同。片上系统还包括可操作地耦合到第一和第二域并且能够将第一域置于第一活动模式中的控制单元，而第二域处于第二活动模式，使得第一域（106）处于第一活动模式和第二区域（108）基本同时处于第二活动模式。第一主动操作模式在功能上不同于第二主动操作模式。

9. 发明申请

WO2010058246A1 MANAGEMENT OF MULTIPLE RESOURCE PROVIDERS 审中-公开
标题翻译：多资源提供者的管理
公开(公告)号：WO2010058246A1
公开(公告)日：2010-05-27
申请号：PCT/IB2008/054917
申请日：2008-11-24
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
发明人： LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
IPC分类号： G06F9/50
CPC分类号： G06F9/505 , G06F2209/5019 , G06F2209/504 , Y02D10/22
摘要： A device (10) receives a request (26) for an amount of a resource. It determines for each resource provider in a set of resource providers (30, 32, 34, 36) a current load (62), a requested load (58) corresponding to the requested amount of the resource, and an additional load (60) corresponding to an expected state (44) of an application. It determines for each of the resource providers (30, 32, 34, 36) an expected total load (52) on the basis of the current load (62), the requested load (58), and the additional load (60). It subsequently selects from the set of resource providers (30, 32, 34, 36) a preferred resource provider (30) on the basis of the expected total loads (52). The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.
摘要翻译：设备（10）接收资源量的请求（26）。它确定一组资源提供者（30,32,34,36）中的每个资源提供者当前负载（62），对应于所请求的资源量的请求负载（58）和附加负载（60）对应于应用的预期状态（44）。它基于当前负载（62），所请求的负载（58）和附加负载（60）来确定每个资源提供者（30,32,34,36）期望的总负载（52）。其随后基于预期的总负载（52）从所述资源提供者集合（30,32,34,36）中选择优选的资源提供者（30）。该资源可能是以下之一：存储器，处理时间，数据吞吐量，功率和设备的使用。

10. 发明申请

WO2014184613A1 MICROCONTROLLER UNIT AND METHOD OF OPERATING A MICROCONTROLLER UNIT 审中-公开
标题翻译：微控制器单元和操作微控制器单元的方法
公开(公告)号：WO2014184613A1
公开(公告)日：2014-11-20
申请号：PCT/IB2013/053883
申请日：2013-05-13
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , FADER, Joachim , LUEPKEN, Harald
发明人： LITOVTCHENKO, Vladimir , FADER, Joachim , LUEPKEN, Harald
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0721 , G06F11/076 , G06F11/079
摘要： A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.
摘要翻译：描述具有功能状态，复位状态和一个或多个可断言故障源的微控制器单元（MCU）。每个故障源都有自己的故障源断言计数和自己的故障源断言限制; MCU被布置为以循环方式执行以下操作序列：如果一个或多个故障源被断言，则从功能状态传递到复位状态，并且将相应的故障源断言计数增加一个增量; 如果一个或多个故障源断言计数超过相应的故障源断言限制，则禁用相应的故障源; 并从复位状态转移到功能状态。还公开了一种操作MCU的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式