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1. 发明申请

WO2008096208A1 REQUEST CONTROLLER, PROCESSING UNIT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：要求控制器，处理单元，控制要求和计算机程序产品的方法
公开(公告)号：WO2008096208A1
公开(公告)日：2008-08-14
申请号：PCT/IB2007/050420
申请日：2007-02-08
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , LITOVTCHENKO, Vladimir
发明人： BOGENBERGER, Florian , LITOVTCHENKO, Vladimir
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit . The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value . The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.
摘要翻译：一种请求控制器，用于控制一个或多个半导体数据处理单元的请求处理。资源控制器包括控制器输入，用于接收处理单元的切换以切换处理单元的上下文或者将处理单元从当前操作切换到另一操作的请求。资源控制器包括其中可以存储一个或多个预算值的资源预算存储器。预算值表示处理单元的资源量。资源控制器还具有预算控制器，其包括连接到请求控制器输入的第一预算控制器输入。第二个预算控制器输入连接到存储器。比较器连接到第一预算控制器输入和第二控制器输入，用于将与请求相关联的消耗值与预算值进行比较。比较器包括比较器输出，用于当比较满足预定的准许标准时输出请求授权信号，并且当比较满足预定的拒绝标准时输出请求拒绝值。数据控制器连接到资源预算存储器和比较器输出端，用于在输出请求授权信号时调整预算值。

2. 发明申请

WO2010058246A1 MANAGEMENT OF MULTIPLE RESOURCE PROVIDERS 审中-公开
标题翻译：多资源提供者的管理
公开(公告)号：WO2010058246A1
公开(公告)日：2010-05-27
申请号：PCT/IB2008/054917
申请日：2008-11-24
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
发明人： LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
IPC分类号： G06F9/50
CPC分类号： G06F9/505 , G06F2209/5019 , G06F2209/504 , Y02D10/22
摘要： A device (10) receives a request (26) for an amount of a resource. It determines for each resource provider in a set of resource providers (30, 32, 34, 36) a current load (62), a requested load (58) corresponding to the requested amount of the resource, and an additional load (60) corresponding to an expected state (44) of an application. It determines for each of the resource providers (30, 32, 34, 36) an expected total load (52) on the basis of the current load (62), the requested load (58), and the additional load (60). It subsequently selects from the set of resource providers (30, 32, 34, 36) a preferred resource provider (30) on the basis of the expected total loads (52). The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.
摘要翻译：设备（10）接收资源量的请求（26）。它确定一组资源提供者（30,32,34,36）中的每个资源提供者当前负载（62），对应于所请求的资源量的请求负载（58）和附加负载（60）对应于应用的预期状态（44）。它基于当前负载（62），所请求的负载（58）和附加负载（60）来确定每个资源提供者（30,32,34,36）期望的总负载（52）。其随后基于预期的总负载（52）从所述资源提供者集合（30,32,34,36）中选择优选的资源提供者（30）。该资源可能是以下之一：存储器，处理时间，数据吞吐量，功率和设备的使用。

3. 发明申请

WO2008099238A1 REQUEST CONTROLLER, PROCESSING UNIT, ARRANGEMENT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：请求控制器，处理单元，安排，控制请求和计算机程序产品的方法
公开(公告)号：WO2008099238A1
公开(公告)日：2008-08-21
申请号：PCT/IB2007/050511
申请日：2007-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
发明人： LITOVTCHENKO, Vladimir , BOGENBERGER, Florian
IPC分类号： G06F13/24 , G06F9/48
CPC分类号： G06F13/24 , G06F9/4812
摘要： A request controller (2) for controlling requests of a processing unit. The request controller may include an request controller input (200-206) for receiving a request and a request processing unit (22) connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current operation to another operation. The request processing unit may decide on the request based on a decision criterion. A request controller output (21 ) may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit (222) including: a state input (2221 ) for receiving information about a current state of a system including the processing unit; and a request input (2220) for receiving information about a received request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit (222) may further include a control logic output (2222) for outputting a request grant signal when the request is granted.
摘要翻译：一种用于控制处理单元的请求的请求控制器（2）。请求控制器可以包括用于接收请求的请求控制器输入（200-206）和连接到请求控制器输入的请求处理单元（22）。请求可以请求切换所述处理单元的上下文或者将处理单元从当前操作切换到另一操作。请求处理单元可以基于判定标准来决定请求。请求控制器输出（21）可以连接到请求处理单元，用于输出关于至少授权请求的信息。所述请求处理单元可以包括：控制逻辑单元（222），包括：状态输入（2221），用于接收关于包括所述处理单元的系统的当前状态的信息; 以及用于接收关于接收到的请求的信息的请求输入（2220）。控制逻辑单元可以被布置为确定接收到的请求是否属于处理器的当前状态，以便当接收到的请求属于当前状态时授予该请求，并且在请求不属于该状态的情况下拒绝该请求当前状态。控制逻辑单元（222）还可以包括用于当请求被授权时输出请求授权信号的控制逻辑输出（2222）。

4. 发明申请

WO2009076033A2 ERROR DETECTOR IN A CACHE MEMORY USING CONFIGURABLE WAY REDUNDANCY 审中-公开
标题翻译：使用可配置方式冗余的高速缓存存储器中的错误检测器
公开(公告)号：WO2009076033A2
公开(公告)日：2009-06-18
申请号：PCT/US2008/084261
申请日：2008-11-21
申请人： FREESCALE SEMICONDUCTOR INC. , REFAELI, Jehoda , BOGENBERGER, Florian , EIFERT, James, B.
发明人： REFAELI, Jehoda , BOGENBERGER, Florian , EIFERT, James, B.
IPC分类号： G06F11/22 , G06F11/26 , G06F11/30
CPC分类号： G06F11/1064 , G06F12/0864 , G06F12/126 , G06F2212/601
摘要： A data processing system (10) includes a processor (12) having a multi-way cache (60) which has a first (64, 72) and a second (66, 74) way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory (18), where the processor (12), in response to a read address missing in the cache (60), provides the read address to the memory (18). The second way may be dynamically configured to be redundant to the first way during operation of the processor (12) in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache (60), data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.
摘要翻译：数据处理系统（10）包括具有第一（64,72）和第二（66,74）方式的多路高速缓存（60）的处理器（12）。第二种方式是配置为第一种方式是冗余的，或作为独立于第一种方式的关联方式运行。系统还可以包括存储器（18），其中响应于高速缓存（60）中缺少的读取地址，处理器（12）向存储器（18）提供读取地址。响应于错误检测信号，在处理器（12）的操作期间，第二种方式可被动态地配置为在第一种方式中是冗余的。在一个方面，当第二种方式被配置为冗余时，响应于高速缓存（60）中的读取地址，由读取地址的索引部分寻址的数据从第一和第二方式提供，并与以确定是否存在比较错误。

5. 发明申请

WO2008053378A1 NETWORK AND METHOD FOR SETTING A TIME-BASE OF A NODE IN THE NETWORK 审中-公开
标题翻译：网络和网络中节点的时基设置方法
公开(公告)号：WO2008053378A1
公开(公告)日：2008-05-08
申请号：PCT/IB2007/051823
申请日：2007-05-14
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , RAUSCH, Mathias
发明人： BOGENBERGER, Florian , RAUSCH, Mathias
IPC分类号： H04J3/06 , H04L12/40
CPC分类号： H04J3/0641
摘要： A data communication network (1 ) may include two or more master clocks (112,122), and a synchronisation system (13) connected to the master clocks. The synchronisation system (13) may determine a time-base for the master clocks. The synchronisation system (13) may control the master clocks according to the determined time-base. The data communication network (1 ) may include one or more slave clocks (22). The slave clocks (22) may be controlled by a slave clock time-base controller (21 ) based on time information of a single selected master clock (112) selected from the master clocks.
摘要翻译：数据通信网络（1）可以包括两个或多个主时钟（112,122）和连接到主时钟的同步系统（13）。同步系统（13）可以确定主时钟的时基。同步系统（13）可以根据确定的时基来控制主时钟。数据通信网络（1）可以包括一个或多个从时钟（22）。从时钟（22）可以由从时钟时基控制器（21）基于从主时钟选择的单个所选主时钟（112）的时间信息来控制。

6. 发明申请

WO2009138819A1 PROCESSING RESOURCE APPARATUS AND METHOD OF SYNCHRONISING A PROCESSING RESOURCE 审中-公开
标题翻译：加工资源设备和同步加工资源的方法
公开(公告)号：WO2009138819A1
公开(公告)日：2009-11-19
申请号：PCT/IB2008/051891
申请日：2008-05-14
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , REIPOLD, Anthony , SAKADA, Oleksandr
发明人： BOGENBERGER, Florian , REIPOLD, Anthony , SAKADA, Oleksandr
IPC分类号： G06F11/27 , G06F11/16
CPC分类号： G01R31/318594 , G06F11/1658
摘要： A processing resource apparatus (100) comprises a reference processing module (102) comprising a set of reference stateful elements and a target processing module (104) comprising a set of target stateful elements. A scan chain (106, 108) having a first mode for supporting manufacture testing is also provided, the scan chain (106, 108) being arranged to couple the reference processing module (102) to the target processing module (104). The scan chain (106, 108) also has a second mode capable of synchronising the set of target stateful elements with the set of reference stateful elements in response to a synchronisation signal.
摘要翻译：处理资源装置（100）包括参考处理模块（102），其包括一组参考状态元素和包括一组目标状态元素的目标处理模块（104）。还提供了具有用于支持制造测试的第一模式的扫描链（106,108），扫描链（106,108）被布置成将参考处理模块（102）耦合到目标处理模块（104）。扫描链（106,108）还具有能够响应于同步信号使目标状态元素集合与该组参考状态元素同步的第二模式。

7. 发明申请

WO2008146091A1 DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND APPARATUS 审中-公开
标题翻译：数据处理系统，数据处理方法和装置
公开(公告)号：WO2008146091A1
公开(公告)日：2008-12-04
申请号：PCT/IB2007/051984
申请日：2007-05-25
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , KRUECKEN, Joaquim , TEMPLE, Christopher
发明人： BOGENBERGER, Florian , KRUECKEN, Joaquim , TEMPLE, Christopher
IPC分类号： G06F11/16
CPC分类号： G06F11/1641 , G06F11/1487 , G06F11/1675 , G06F15/7842 , G06F2201/845
摘要： A data processing system (1 ) may include a first data path (100) and a second data path (101 ). A set (2) of components (200,210,220,230) may include a system component (200,220) and a partner component (210,230), each having a communication interface (201 ,211 ,221 ,231 ) for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system (240) connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non- synchronized mode configuration. The configuration control system may include a first path selector module (241 ,243) connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module (242,244) connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.
摘要翻译：数据处理系统（1）可以包括第一数据路径（100）和第二数据路径（101）。一组（2）的组件（200,210,220,230）可以包括系统组件（200,220）和伙伴组件（210,230），每个组件具有用于传送数据的通信接口（201,211,221,231）。组件可以相对于彼此以同步模式和非同步模式操作。该组还可以包括连接到系统组件和伙伴组件的配置控制系统（240），用于控制组处于同步模式配置或非同步模式配置。配置控制系统可以包括将系统组件的通信接口连接到第一数据路径和第二数据路径的第一路径选择器模块（241,243）和连接对方的通信接口的伙伴路径选择器模块（242,244）分量到第一数据路径和第二数据路径。路径选择器模块可以被布置成使得根据配置能够经由从第一数据路径和第二数据路径选择的一个或多个所选择的数据路径将数据传送到相应的组件，并且通过未选择的方式禁止通信数据路径。

8. 发明申请

WO2008053277A1 NETWORK AND METHOD FOR SETTING A TIME-BASE OF A NODE IN THE NETWORK 审中-公开
标题翻译：网络和网络中节点的时基设置方法
公开(公告)号：WO2008053277A1
公开(公告)日：2008-05-08
申请号：PCT/IB2006/054024
申请日：2006-10-31
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , RAUSCH, Mathias
发明人： BOGENBERGER, Florian , RAUSCH, Mathias
IPC分类号： H04J3/06 , H04L12/40
CPC分类号： H04J3/0641
摘要： A data communication network (1 ) may, include a first sub-network (2) and a second sub- network (3). The first sub-network (2) may include two or more two master clocks (112,122), and a synchronisation system (13) connected to the master clocks. The synchronisation system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network (2) may include one or more slave synchronisation data source (1 13, 123) for generating slave clock synchronisation data derived from time information of the master clocks. The second sub-network may include one or more slave clocks (22) and a slave clock time-base controller (21 ) connected to the slave synchronisation data source. The time-base controller (21 ) may receive the slave clock synchronisation data and control one or more of the one or more slave clocks in accordance with the slave clock synchronisation data.
摘要翻译：数据通信网络（1）可以包括第一子网（2）和第二子网（3）。第一子网（2）可以包括两个或更多个主时钟（112,122）和连接到主时钟的同步系统（13）。同步系统可以用于确定主时钟的时基并且基于确定的时基来控制主时钟。第一子网（2）可以包括用于产生从主时钟的时间信息导出的从时钟同步数据的一个或多个从同步数据源（13,133）。第二子网可以包括连接到从同步数据源的一个或多个从时钟（22）和从时钟时基控制器（21）。时基控制器（21）可以根据从时钟同步数据接收从时钟同步数据并控制一个或多个从时钟中的一个或多个。

9. 发明申请

WO2010038096A1 METHOD AND APPARATUS FOR HANDLING AN OUTPUT MISMATCH 审中-公开
标题翻译：用于处理输出误差的方法和装置
公开(公告)号：WO2010038096A1
公开(公告)日：2010-04-08
申请号：PCT/IB2008/053966
申请日：2008-09-30
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , TEMPLE, Christopher
发明人： BOGENBERGER, Florian , TEMPLE, Christopher
IPC分类号： G06F11/16
CPC分类号： G06F11/1641 , G06F11/1497 , G06F11/165 , G06F11/1658 , G06F11/1675
摘要： A system (100) comprises a first signal processing logic module (115) and at least one further signal processing logic module (125). The system (100) further comprises mismatch handler logic module (150) arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module (115, 125), t he mismatch between outputs indicating a failed operation. The mismatch handler logic module fu rther arranged, upon detection of a mismatch between outputs of the first and at least one furthe r signal processing logic module (115, 125), to analyse internal states of the first and at least one further signal processing logic module (115, 125), determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of t he output mismatch is due to a transient fault, to re-synchronise the first and at least one further signal processing logic module (115, 125).
摘要翻译：系统（100）包括第一信号处理逻辑模块（115）和至少一个另外的信号处理逻辑模块（125）。系统（100）还包括不匹配处理器逻辑模块（150），其布置成检测第一和至少一个另外的信号处理逻辑模块（115,125）的输出之间的失配，指示失败操作的输出之间的失配。不匹配处理器逻辑模块在检测到第一和至少一个信号处理逻辑模块（115,125）的输出之间的不匹配时被布置，以分析第一和至少一个另外的信号处理逻辑的内部状态模块（115,125）确定输出不匹配的原因是由于瞬态故障，并且在确定输出失配的原因是由于瞬态故障引起的，以使第一和至少一个进一步的信号处理逻辑模块（115,125）。

10. 发明申请

WO2009141684A1 DISPLAY CONTROLLER, IMAGE PROCESSING SYSTEM, DISPLAY SYSTEM, APPARATUS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：显示控制器，图像处理系统，显示系统，装置和计算机程序产品
公开(公告)号：WO2009141684A1
公开(公告)日：2009-11-26
申请号：PCT/IB2008/051976
申请日：2008-05-20
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , BOGAVAC, Davor
发明人： BOGENBERGER, Florian , BOGAVAC, Davor
IPC分类号： B60K35/00 , H04N17/00 , G06T7/00
CPC分类号： B60K35/00 , B60K2350/1072 , B60K2350/2056 , G06F3/14 , G09G5/026 , G09G5/14 , G09G2330/12 , G09G2340/12 , G09G2380/10
摘要： A display controller (3) includes a controller input (300,301 ) connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display (5) and to receive second image data representing a safety relevant part of the image. A merging unit (31 ) is connected to the controller input (300,301 ), for composing the image from the first image data and second image data. A controller output (33) is connectable to the display, for outputting display data representing the image. An image monitor (4) is connected to the controller output (33), for comparing a part of the image corresponding to the safety relevant part with an reference for the part.
摘要翻译：显示控制器（3）包括可连接以接收表示要在显示器（5）上显示的图像的非安全相关部分的第一图像数据的控制器输入（300,301），并且接收表示在显示器（5）上显示的图像的安全相关部分的第二图像数据图片。合并单元（31）连接到控制器输入（300,301），用于从第一图像数据和第二图像数据构成图像。控制器输出（33）可连接到显示器，用于输出表示图像的显示数据。图像监视器（4）连接到控制器输出（33），用于将与安全相关部分相对应的图像的一部分与该部分的参考进行比较。

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