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1. 发明申请

WO2005112094A9 METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 审中-公开
公开(公告)号：WO2005112094A9
公开(公告)日：2005-11-24
申请号：PCT/US2005/011552
申请日：2005-04-05
申请人： FREESCALE SEMICONDUCTOR, INC. , ORLOWSKI, Marius K. , BARR, Alexander L. , SADAKA, Mariam G. , WHITE, Ted R.
发明人： ORLOWSKI, Marius K. , BARR, Alexander L. , SADAKA, Mariam G. , WHITE, Ted R.
IPC分类号： H01L21/31
摘要： A semiconductor substrate having a silicon layer (24,26,28) is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate (12,14,24,26,28) having an oxide layer (14) underlying the silicon layer (24,26,28). An amorphous or polycrystalline silicon germanium layer (32) is formed overlying the silicon layer (24,26,28). Alternatively, germanium is implanted into a top portion of the silicon layer (24,26,28) to form an amorphous silicon germanium layer (32). The silicon germanium layer (32) is then oxidized to convert the silicon germanium layer into a silicon dioxide layer (34) and to convert at least a portion of the silicon layer (24,26,28) into germanium-rich silicon (36,38). The silicon dioxide layer (34) is then removed prior to forming transistors (48,50,52) using the germanium-rich silicon (36,38). In one embodiment, the germanium-rich silicon (36,38) is selectively formed using a patterned masking layer (30) over the silicon layer (28) and under the silicon germanium layer (32). Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

2. 发明申请

WO2006023492A1 GRADED SEMICONDUCTOR LAYER 审中-公开
标题翻译：分级半导体层
公开(公告)号：WO2006023492A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/029113
申请日：2005-08-08
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , THOMAS, Shawn G. , WHITE, Ted R. , LIU, Chun-Li , BARR, Alexander L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
发明人： SADAKA, Mariam G. , THOMAS, Shawn G. , WHITE, Ted R. , LIU, Chun-Li , BARR, Alexander L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer (207) for forming a layer (305) of strained silicon. In one example a layer (107) of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层（305）的模板层（207）。在一个示例中，形成梯度硅锗的层（107），其中锗在下部具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

3. 发明申请

WO2006107419A3 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006107419A3
公开(公告)日：2006-10-12
申请号：PCT/US2006/005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
发明人： SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
IPC分类号： H01L21/8238
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

4. 发明申请

WO2006039038A2 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 审中-公开
标题翻译：形成具有应变通道和异常源/漏极的半导体器件的方法
公开(公告)号：WO2006039038A2
公开(公告)日：2006-04-13
申请号：PCT/US2005/031001
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

5. 发明申请

WO2008014031A3 TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY 审中-公开
公开(公告)号：WO2008014031A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/068086
申请日：2007-05-03
申请人： FREESCALE SEMICONDUCTOR INC. , WHITE, Ted R. , BURNETT, James D. , WINSTEAD, Brian A.
发明人： WHITE, Ted R. , BURNETT, James D. , WINSTEAD, Brian A.
IPC分类号： H01L21/8244 , H01L21/336 , H01L27/11 , H01L29/772
摘要： A transistor (22) having a source with higher resistance than its drain is optimal as a load transistor (20) in a static random access memory circuit (10). The transistor has a source region with a source implant (38) having a source resistance (24). A gate electrode (50) is adjacent the source region for controlling electrical conduction of the transistor. The drain region is adjacent the gate electrode region and opposite the source region. The drain region has a drain implant (40, 58) that can be salicided (51) and has a drain resistance. The source resistance is more than the drain resistance because the source region has a physical property that differs from the drain region. The different physical property can be created by saliciding only one of the drain or source regions, using differing doping concentrations and/or energies when implanting the source/drain regions, having differing sizes for the source and drain regions, positioning the source further away from the gate electrode region than the drain region, using different dopants for the source and drain regions, or removing a portion of the source implant region and replacing it with an in-situ doped semiconductor material such as aluminium phosphide, gallium phosphide and zinc sulphide.

6. 发明申请

WO2007130151A2 SOI ACTIVE LAYER WITH DIFFERENT SURFACE ORIENTATION 审中-公开
标题翻译：具有不同表面方位的SOI主动层
公开(公告)号：WO2007130151A2
公开(公告)日：2007-11-15
申请号：PCT/US2006/061274
申请日：2006-11-28
申请人： FREESCALE SEMICONDUCTOR INC. , ADETUTU, Olubunmi O. , JONES, Robert E. , WHITE, Ted R.
发明人： ADETUTU, Olubunmi O. , JONES, Robert E. , WHITE, Ted R.
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures (201, 203, 205) having a first surface orientation are formed on a donor wafer (101). Semiconductor structures (401, 403, 405) having a second surface orientation are formed on a second wafer (301). Receptor openings are formed on the second wafer (301). The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片（101）上形成具有第一表面取向的半导体结构（201,203,205）。具有第二表面取向的半导体结构（401,403,405）形成在第二晶片（301）上。受体开口形成在第二晶片（301）上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

7. 发明申请

WO2006104549A1 DUAL METAL GATE ELECTRODE SEMICONDUCTOR FABRICATION PROCESS AND STRUCTURE THEREOF 审中-公开
标题翻译：双金属电极电极半导体制造工艺及其结构
公开(公告)号：WO2006104549A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/002648
申请日：2006-01-25
申请人： FREESCALE SEMICONDUCTOR, INC. , WHITE, Ted R. , ADETUTU, Olubunmi O. , JONES, Robert E.
发明人： WHITE, Ted R. , ADETUTU, Olubunmi O. , JONES, Robert E.
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L21/8238 , H01L27/01 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119 , H01L31/0392 , H01L31/113
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer (112) overlying a gate dielectric (110). A second gate electrode layer (120) is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer (130) may be formed overlying the first and second gate electrode layers. The first gate electrode layer (112) may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer (120) may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer (120) may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer (120).
摘要翻译：半导体制造工艺包括图案化覆盖在栅极电介质（110）上的第一栅电极层（112）。第二栅极电极层（120）形成在第一栅极电极层和栅极电介质上。去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。可以形成第三栅极电极层（130），覆盖第一和第二栅电极层。第一栅极电极层（112）可以包括TiN并且主要驻留在PMOS区域上，而第二栅电极层（120）可以包括TaC或TaSiN，并且主要覆盖NMOS区域。去除第二栅极电极层（120）的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层（120）的暴露部分的情况下执行化学机械处理（CMP）。

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