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1. 发明申请

WO2006102141A2 EFFICIENT CHECK NODE MESSAGE TRANSFORM APPROXIMATION FOR LDPC DECODER 审中-公开
标题翻译：有效检查LDPC解码器的节点信息变换近似
公开(公告)号：WO2006102141A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/009839
申请日：2006-03-17
申请人： QUALCOMM FLARION TECHNOLOGIES, INC. , NOVICHKOV, Vladimir , RICHARDSON, Tom
发明人： NOVICHKOV, Vladimir , RICHARDSON, Tom
CPC分类号： H03M7/24 , H03M13/1117 , H03M13/112 , H03M13/1125 , H03M13/6577 , H03M13/658
摘要： In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log / exp instructions and especially on a SIMD FPU-equipped processors where log / exp functions are typically scalar.
摘要翻译：在诸如可以使用本发明的LDPC解码器和turbo卷积解码器的现代迭代编码系统中，核心计算通常可以减少到在对数和线性域之间交替的加法和减法序列。计算有效和鲁棒的近似方法描述了log和exp函数，其涉及使用固定点分数据格式和浮点格式之间的简单位映射。该方法避免了昂贵的查找表和复杂的计算，并且使用交替的固定点和浮点处理单元进一步将核心处理减少到一系列的加法和减法。该方法非常适合用于高度优化的硬件实现，可以利用标准浮点运算电路设计的现代进步以及配备FPU的广泛类型处理器上的软件实现，其中本发明避免了对典型多周期系列的log / exp指令，特别是在一个SIMD FPU处理器上，其中log / exp函数通常是标量的。

2. 发明申请

WO2003032499A1 NODE PROCESSORS FOR USE IN PARITY CHECK DECODERS 审中-公开
标题翻译：使用异常检查代码的节点处理器
公开(公告)号：WO2003032499A1
公开(公告)日：2003-04-17
申请号：PCT/US2002/031971
申请日：2002-10-07
申请人： FLARION TECHNOLOGIES, INC. , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H03M13/00
CPC分类号： H03M13/1137 , G06N3/02 , H03M13/1102 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/1125 , H03M13/1131 , H03M13/1134 , H03M13/1145 , H03M13/6362 , H03M13/6502 , H03M13/6577 , H03M13/658 , H03M13/6583
摘要： Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ? ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module (1302), subtractor module (1304) and delay pipeline (1306). The accumulator module (1302) generates an accumulated message sum (1316). The accumulated message sum (1316) for a node is stored and then delayed input messages from the delay pipeline (1306) are subtracted there from to generate output messages (1321). The delay pipeline (1306) includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.
摘要翻译：描述了用于实现消息传递解码器（例如，LDPC解码器）的技术。为了便于硬件实现，消息被量化为¼n2的整数倍。消息在更紧凑的可变和不紧凑的约束节点消息表示格式之间转换。变量节点消息格式允许通过简单的加法和减法执行变量节点消息操作，而约束节点表示允许通过简单的加法和减法执行约束节点消息处理。可变和约束节点使用累加器模块（1302），减法器模块（1304）和延迟流水线（1306）来实现。累加器模块（1302）生成累积消息和（1316）。存储节点的累积消息和（1316），然后将来自延迟流水线（1306）的延迟输入消息从那里减去以产生输出消息（1321）。延迟管线（1306）包括可变延迟元件，使得可以顺序地执行与不同程度的节点对应的处理操作。

3. 发明申请

WO2004091125A2 METHODS AND APPARATUS FOR INTERLEAVING IN A BLOCK-COHERENT COMMUNICATION SYSTEM 审中-公开
标题翻译：用于在块通信系统中交互的方法和装置
公开(公告)号：WO2004091125A2
公开(公告)日：2004-10-21
申请号：PCT/US2004/010186
申请日：2004-04-02
申请人： FLARION TECHNOLOGIES, INC. , JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H04J
CPC分类号： H03M13/116 , H03M13/2757 , H03M13/2957 , H03M13/6331
摘要： Methods and apparatus for communication over a block-coherent communication system are described. The present invention is directed to methods of interleaving coded bits that are encoded by codes, e.g., LDPC codes, having graph structures largely comprised, e.g., of multiple identical copies of a much smaller graph.
摘要翻译：描述了通过块相干通信系统进行通信的方法和装置。本发明涉及交织由码（例如，LDPC码）编码的编码比特的方法，所述编码比特具有主要由例如更小图的多个相同副本组成的图形结构。

4. 发明申请

WO2004079563A1 SOFT INFORMATION SCALING FOR ITERATIVE DECODING 审中-公开
标题翻译：用于迭代解码的软信息分级
公开(公告)号：WO2004079563A1
公开(公告)日：2004-09-16
申请号：PCT/US2003/024730
申请日：2003-08-07
申请人： FLARION TECHNOLOGIES, INC. , RICHARDSON, Tom , NOVICHKOV, Vladimir , JIN, Hui
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir , JIN, Hui
IPC分类号： G06F7/60
CPC分类号： H04L1/005 , H03M13/00 , H03M13/1102 , H03M13/296 , H03M13/3707 , H03M13/6325 , H03M13/658
摘要： Methods and apparatus for scaling soft values (214) as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for prior knowledge of the correct scale factor or the actual channel conditions at the time the signal from which the soft values were obtained was transmitted through a communications channel. The techniques of the present invention assumes that the soft values to be processed were transmitted through a communications channel having a quality that can be accurately described by a channel quality value (200). A scale factor is determined from the distribution of soft value (208) to be scaled (212) and an assumption that the channel through which they were transmitted was of the quality corresponding to a pre-selected channel quality value (210).
摘要翻译：描述作为纠错解码处理的一部分来缩放软值（214）的方法和装置。精确的解码取决于使用适当的比例因子。设计用于缩放软值的比例因子的选择和使用被设计为改善和/或优化解码器性能，而不需要在获得软值的信号时获得正确比例因子或实际信道条件的先验知识通过通信信道传输。本发明的技术假设要通过通道信道发送待处理的软值，该通信信道具有可以通过信道质量值（200）精确描述的质量。根据要缩放的软值（208）的分布来确定比例因子（212），以及假设其被发送的信道具有与预先选择的信道质量值对应的质量（210）。

5. 发明申请

WO2006017555A2 MEMORY EFFICIENT LDPC DECODING METHODS AND APPARATUS 审中-公开
标题翻译：存储有效的LDPC解码方法和设备
公开(公告)号：WO2006017555A2
公开(公告)日：2006-02-16
申请号：PCT/US2005/027526
申请日：2005-08-01
申请人： FLARION TECHNOLOGIES, INC. , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H03M13/00
CPC分类号： H03M13/6362 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/1137
摘要： Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.
摘要翻译：描述了实现存储器高效LDPC解码的方法和装置。根据本发明，消息信息以压缩状态存储以进行校验节点处理操作。检查节点的状态被完全更新，然后进行提取处理，以生成可变节点消息的校验节点。从可变节点接收的消息的符号可以由本发明的校验节点处理器模块存储以用于消息提取。校验节点处理器可以以可变节点顺序处理消息，从而允许变量节点处理器和校验节点处理器以相同的顺序对消息进行操作，以减少或消除在校验节点和可变节点之间传递的消息的缓冲和/或重新排序的需要。还描述了允许在先前的图形迭代完成之前在一个图形迭代上进行校验节点处理的图形结构。

6. 发明申请

WO2004091102A1 EXTRACTING SOFT INFORMATION IN A BLOCK-COHERENT COMMUNICATION SYSTEM 审中-公开
标题翻译：提取软通信系统中的软件信息
公开(公告)号：WO2004091102A1
公开(公告)日：2004-10-21
申请号：PCT/US2004/010187
申请日：2004-04-02
申请人： FLARION TECHNOLOGIES INC , JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H03M13/29 , H03M13/2957 , H03M13/31 , H03M13/3784 , H03M13/45 , H03M13/6325 , H04L1/0045 , H04L1/0065 , H04L1/0071
摘要： Data communication over a block-coherent channel in a communication system is described. Low-complexity demodulation techniques that allow good performance are described. A dwell syn signal (323), e.g., a set of block coherent symbols transmitted including a known symbol, e.g., a pseudo pilot symbol, are received, demodulated (204) and decoded by a joint decoder/demodulator (311 and 313) employing soft inputs, soft outputs, and interleaving of messages. Low-complexity SISO demodulator (204) is suitable for processing pseudo-pilot modulated information corresponding to each of one or more dwells (323). The low-complexity method achieves good performance when turbo equalization is used. Some decoding and demodulation embodiments include independent phase estimates and updated independent phase estimates following the extrinsic principle to generate soft symbol values and soft bits.
摘要翻译：描述通信系统中的块相干信道的数据通信。描述了允许良好性能的低复杂度解调技术。驻留同步信号（323），例如包括已知符号（例如，伪导频符号）的一组块相干符号被接收，解码（204）并通过采用如下的联合解码器/解调器（311和313）进行解码软输入，软输出和消息的交织。低复杂度SISO解调器（204）适于处理对应于一个或多个住宅中的每一个的伪导频调制信息（323）。当使用turbo均衡时，低复杂度方法实现了良好的性能。一些解码和解调实施例包括独立的相位估计和更新的独立相位估计之后，产生软符号值和软比特的外在原理。

7. 发明申请

WO2004019268A1 METHODS AND APPARATUS FOR ENCODING LDPC CODES 审中-公开
标题翻译：编码LDPC码的方法和装置
公开(公告)号：WO2004019268A1
公开(公告)日：2004-03-04
申请号：PCT/US2002/040573
申请日：2002-12-18
申请人： FLARION TECHNOLOGIES, INC. , JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： JIN, Hui , RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： G06N
CPC分类号： H03M13/6561 , H03M13/1102 , H03M13/1137 , H03M13/116 , H03M13/1182
摘要： Methods and apparatus for encoding (1812) codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures (1202) which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory (1006) and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction (1004). The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.
摘要翻译：描述了特别适用于低密度奇偶校验（LDPC）码和长码字的编码（1812）码字的方法和装置。所描述的方法允许编码图形结构（1202），其主要由较小图的多个相同副本组成。较小图的副本经受受控置换操作以创建较大的图形结构。直接实现相同的受控置换，以支持小图的复制副本之间的位传递。对应于图的各个副本的位被存储在存储器（1006）中，并且使用SIMD读或写指令（1004）以组合的方式从图的每个副本中进行访问。图形置换操作可以通过在比特存储器中读出的每组比特中简单地重新排序比特，例如使用循环置换操作来实现，使得比特被传递到对应于小图的不同副本的处理电路。

8. 发明申请

WO2002103631A1 METHODS AND APPARATUS FOR DECODING LDPC CODES 审中-公开
标题翻译：用于解码LDPC码的方法和装置
公开(公告)号：WO2002103631A1
公开(公告)日：2002-12-27
申请号：PCT/US2002/017396
申请日：2002-05-31
申请人： FLARION TECHNOLOGIES, INC. , RICHARDSON, Tom , NOVICHKOV, Vladimir
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： G06N3/00
CPC分类号： H03M13/6356 , G06N3/02 , H03M13/1114 , H03M13/1131 , H03M13/1137 , H03M13/1148 , H03M13/116 , H03M13/1168 , H03M13/1177 , H03M13/6362 , H03M13/6505 , H03M13/6566
摘要： Methods and apparatus for decoding codewords (902) using message passing decoding techniques which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow decoding graph structures which are largely comprised of multiple identical copies of a much smaller graph (1000). Copies of the smaller graph are subject to a controlled permutation operation (904) to create the larger graph structure. The same controlled permutations are directly implemented to support message passing between the replicated copies of the small graph. Messages corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering messages, e.g., using a cyclic permutation operation, in each set of messages react out of a message memory so that the messages are passed to processing circuits corresponding to different copies of the small graph.
摘要翻译：描述了使用特别适用于低密度奇偶校验（LDPC）码和长码字的消息传递解码技术来解码码字（902）的方法和装置。所描述的方法允许解码图形结构，其大部分由更小的图形的多个相同副本组成（1000）。较小图的副本经受受控置换操作（904）以创建较大的图形结构。直接实现相同的受控置换，以支持小图的复制副本之间的消息传递。与图形的各个副本相对应的消息存储在存储器中，并使用SIMD读或写指令从集合的每个副本中进行访问。图形置换操作可以通过简单地重新排序消息来实现，例如，使用循环置换操作，每组消息从消息存储器中反应，使得消息被传递到对应于小图的不同副本的处理电路。

9. 发明申请

WO2006098748A2 LDPC DECODING METHODS AND APPARATUS 审中-公开
标题翻译： LDPC解码方法和设备
公开(公告)号：WO2006098748A2
公开(公告)日：2006-09-21
申请号：PCT/US2005/025879
申请日：2005-07-20
申请人： FLARION TECNOLOGIES, INC. , RICHARDSON, Tom , JIN, Hui , NOVICHKOV, Vladimir
发明人： RICHARDSON, Tom , JIN, Hui , NOVICHKOV, Vladimir
IPC分类号： H03M13/00
CPC分类号： H04L1/0057 , H03M13/1137 , H03M13/116 , H03M13/6513 , H03M13/6516 , H04L1/0045
摘要： A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.
摘要翻译：描述了一种灵活且相对硬件有效的LDPC解码器。该解码器可以用低于用于控制解码过程的代码结构的完全并行性的并行级别来实现。用于描述代码结构的相对简单的控制代码的每个命令可以被多次存储和执行以完成码字的解码。使用相同的一组控制码指令支持不同的码字长度，但是根据码字长度，代码被实现不同的次数。解码器可以通过简单地改变表示码字长度的代码提升因子而不需要改变存储的代码描述信息来切换不同长度的解码码字，并用于控制解码过程。当解码短于最大支持码字长度的码字时，一些块存储位置可能不被使用。

10. 发明申请

WO2007075773A2 METHODS AND APPARATUS FOR COMMUNICATING CONTROL INFORMATION 审中-公开
标题翻译：传播控制信息的方法和装置
公开(公告)号：WO2007075773A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/048584
申请日：2006-12-20
申请人： QUALCOMM FLARION TECHNOLOGIES, INC. , RICHARDSON, Tom , JIN, Hui , LI, Junyi , PARIZHSKY, Vladimir
发明人： RICHARDSON, Tom , JIN, Hui , LI, Junyi , PARIZHSKY, Vladimir
IPC分类号： H04W28/18 , H04W52/08 , H04W52/14
CPC分类号： H04L27/2602 , H04L1/0004 , H04L27/2627 , H04W28/18 , H04W52/08 , H04W52/146 , H04W72/0413
摘要： In a first mode of dedicated control channel (DCCH) operation, a wireless terminal is allocated more segments than in a second mode. The wireless terminal uses different information bit to modulation symbol mapping in the different modes. On a per DCCH segment basis, the same number of modulation symbols are communicatd in either mode but more information bits are conveyed in the second mode. Information bits for a DCCH segment are partitioned into two subsets. The two subsets are used to generate another set, each of the two subsets and the another set are input to the same mapping function to generate three equal size sets of modulation symbols which are transmitted via the DCCH segment. Uplink tone hopping is used such that one of the equal size sets of modulation symbols for the DCCH segment uses the same tone but a different set uses a different tone.
摘要翻译：在专用控制信道（DCCH）操作的第一模式中，与第二模式相比，无线终端被分配更多的分组。无线终端在不同模式下使用不同的信息比特来调制符号映射。在每个DCCH段的基础上，相同数量的调制符号以任一模式通信，但在第二模式中传送更多的信息位。 DCCH段的信息位被划分成两个子集。这两个子集用于生成另一集合，两个子集中的每一个和另一集合被输入到相同的映射函数，以生成经由DCCH段发送的三个相等大小的调制符号组。使用上行链路跳频使得用于DCCH段的相等大小的调制符号组之一使用相同的音调，但是不同的组使用不同的音调。

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