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1. 发明申请

WO2010059333A3 SEMICONDUCTOR DIE STRUCTURES FOR WAFER-LEVEL CHIPSCALE PACKAGING OF POWER DEVICES, PACKAGES AND SYSTEMS FOR USING THE SAME, AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：用于功率器件的晶片级芯片封装的半导体模结构，以及使用它的封装和系统以及制造该器件的方法
公开(公告)号：WO2010059333A3
公开(公告)日：2010-07-22
申请号：PCT/US2009061879
申请日：2009-10-23
申请人： FAIRCHILD SEMICONDUCTOR , GRUENHAGEN MICHAEL D , KIM SUKU , MURPHY JAMES J , HO IHSIU , TJHIA EDDY , WU CHUNG-LIN , LARSEN MARK , DIKSHIT ROHIT
发明人： GRUENHAGEN MICHAEL D , KIM SUKU , MURPHY JAMES J , HO IHSIU , TJHIA EDDY , WU CHUNG-LIN , LARSEN MARK , DIKSHIT ROHIT
IPC分类号： H01L23/48
CPC分类号： H01L23/36 , H01L23/3114 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L29/7802 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使得具有垂直功率器件的管芯能够被封装在晶片级芯片规模封装中，其中导电端子存在于管芯的一个表面处，并且其中器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔口形成在管芯的背侧中，其中孔口接触管芯顶表面处的导电区域。导电层和/或导电体可以设置在沟槽和开口上以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的包装和系统，以及使用根据本发明的模具结构来制造模具的方法。

2. 发明申请

WO2010144375A3 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件的3D通道架构
公开(公告)号：WO2010144375A3
公开(公告)日：2011-03-03
申请号：PCT/US2010037656
申请日：2010-06-07
申请人： FAIRCHILD SEMICONDUCTOR , KIM SUKU , CALAFUT DAN , HO IHSIU , KINZER DAN , SAPP STEVEN , CHALLA ASHOK , JO SEOKJIN , LARSEN MARK
发明人： KIM SUKU , CALAFUT DAN , HO IHSIU , KINZER DAN , SAPP STEVEN , CHALLA ASHOK , JO SEOKJIN , LARSEN MARK
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

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