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1. 发明申请

WO2018200298A1 DELAYED WRITE-BACK IN MEMORY WITH CALIBRATION SUPPORT 审中-公开
公开(公告)号：WO2018200298A1
公开(公告)日：2018-11-01
申请号：PCT/US2018/028250
申请日：2018-04-19
申请人： EVERSPIN TECHNOLOGIES, INC.
发明人： ALAM, Syed, M.
IPC分类号： G11C16/22
摘要： A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After ail initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed. Calibration and testing sequences are also supported in which a non-destructive mode preserves data stored in a non-volatile memory array and status bits used to indicate open pages are cleared so later inadvertent delayed write-back operations as a result of the calibration or testing do not corrupt the non- volatile data.

2. 发明申请

WO2022094047A2 SYSTEMS AND METHODS FOR MONITORING AND MANAGING MEMORY DEVICES 审中-公开
公开(公告)号：WO2022094047A2
公开(公告)日：2022-05-05
申请号：PCT/US2021/057008
申请日：2021-10-28
申请人： EVERSPIN TECHNOLOGIES, INC.
发明人： ALAM, Syed, M. , JANESKY, Jason , LEE, Han, Kyu , ALMASI, Hamid , SANCHEZ, Pedro , MASGRAS, Cristian, P. , RAHMAN, Iftekhar , IKEGAWA, Sumio , AGGARWAL, Sanjeev , HOUSSAMEDDINE, Dimitri , NEUMEYER, Frederick, Charles
IPC分类号： G06F11/16 , G06F11/1666 , G11C2029/0407 , G11C2029/1202 , G11C29/1201 , G11C29/18 , G11C29/42 , G11C29/4401
摘要： The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

3. 发明申请

WO2014059082A2 MEMORY DEVICE WITH REDUCED ON-CHIP NOISE 审中-公开
标题翻译：存储器件具有降低的片上噪声
公开(公告)号：WO2014059082A2
公开(公告)日：2014-04-17
申请号：PCT/US2013/064242
申请日：2013-10-10
申请人： ANDRE, Thomas , ALAM, Syed, M. , GOGL, Dietmar , EVERSPIN TECHNOLOGIES, INC.
发明人： ANDRE, Thomas , ALAM, Syed, M. , GOGL, Dietmar
IPC分类号： G11C7/02 , G11C5/14
CPC分类号： G11C7/02 , G11C5/14 , G11C5/145 , G11C5/146 , G11C5/147 , G11C7/06 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C16/12 , G11C16/30
摘要： In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.
摘要翻译：在一些示例中，存储装置包括配备有隔离开关和专用电源引脚的多个存储体。每个存储体的隔离开关配置为将存储体与全局信号隔离。专用电源引脚被配置为将每个存储体连接到封装衬底上的专用本地电源焊盘，以向每个存储体提供本地专用电源并且减少设备上的导体上的存储体之间的电压传输，器件衬底或存储器件的封装衬底。

4. 发明申请

WO2016053985A1 SHORT DETECTION AND INVERSION 审中-公开
标题翻译：短期检测和反转
公开(公告)号：WO2016053985A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/052855
申请日：2015-09-29
申请人： EVERSPIN TECHNOLOGIES, INC.
发明人： ANDRE, Thomas , SLAUGHTER, Jon , HOUSSAMEDDINE, Dimitri , ALAM, Syed, M.
IPC分类号： G06F11/10
CPC分类号： G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
摘要翻译：在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配位单元格。

5. 发明申请

WO2016049418A1 ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY 审中-公开
标题翻译： ECC字配置系统级ECC兼容性
公开(公告)号：WO2016049418A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052151
申请日：2015-09-25
申请人： EVERSPIN TECHNOLOGIES, INC.
发明人： ALAM, Syed, M. , ANDRE, Thomas
IPC分类号： G06F11/10
CPC分类号： H03M13/2906 , G06F11/1012 , G06F11/1076
摘要： In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be perform. ed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.
摘要翻译：在一些示例中，存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正的纠错可能会执行。在特定时间段内由每个输入/输出焊盘输出的数据。存储器件的一个或多个输入/输出焊盘中的每一个可被配置为在从外部源访问期间仅向外部源提供每个ECC字的一位数据。

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