会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • MULTI-CHANNEL AMPLIFIER WITH CONTINUOUS CLASS-D MODULATOR AND EMBEDDED PLD AND RESONANT FREQUENCY DETECTOR
    • 具有连续D类调制器和嵌入式PLD和谐振频率检测器的多通道放大器
    • WO2017132594A3
    • 2017-08-03
    • PCT/US2017/015476
    • 2017-01-27
    • DOLBY LABORATORIES LICENSING CORPORATION
    • HEALY, AndrewVOGEL, Erich H.POULAIN, Andrew M.LONG, Gregory J.BUTLER, Joel A.LUCE, Angela S.REVELLI, LucaNURMUKHANOV, DossymCOOK, TannerTRAVERSO M., Marcelo
    • H03F3/217H04S7/00H04R5/00H04R29/00H03G3/30H03G3/00H03F3/68H04R5/04H02M1/32H02M1/42H05B37/02H02M1/00H03F3/181
    • A continuous time Class-D modulator with an embedded programmable logic device in a forward path. The FPGA is configured to provide synchronization control by deriving a synchronization clock for the modulator and monitoring a 1-bit PWM signal for sync-lock status; monitoring the PWM duty cycle to detect overage conditions and lowering audio levels to eliminate hard-clipping events; implementing dead-band timing for subsequent output stages; dynamically controlling the net loop delay seen by the 1-bit PWM using programmable delay lines; monitoring amplifier output conditions to provide comparison with the 1-bit PWM or determine load characteristics; monitoring a front-end integrator to trim for optimal distortion (THD+N). An output circuit of an audio amplifier having an analog filter stage comprising an inductor/capacitor (LC) circuit, a physical connector for connecting a speaker, a tuned resonant circuit configured to provide a low-impedance load for the output circuit in the event of an open load on the output circuit by providing damping of a natural resonance of the LC circuit or of high-frequency oscillations in the output circuit, and a resonant frequency detection coupled to the output of the LCR circuit to detect one of a natural resonance oscillation or the high- frequency oscillation condition. The tuned resonant circuit provides modulation control to a closed-loop Class D amplifier with feedback after the output filter.
    • 具有嵌入式可编程逻辑器件的连续时间D类调制器在前向路径中。 FPGA配置为通过为调制器派生同步时钟并监视1位PWM信号以实现同步锁定状态来提供同步控制; 监测PWM占空比以检测过量状况并降低音频电平以消除硬限幅事件; 为后续输出阶段实现死区定时; 使用可编程延迟线动态控制由1位PWM看到的网络环路延迟; 监视放大器的输出条件,以提供与1位PWM进行比较或确定负载特性; 监视前端积分器进行调整以获得最佳失真(THD + N)。 一种音频放大器的输出电路,具有包括电感器/电容器(LC)电路的模拟滤波器级,用于连接扬声器的物理连接器,被配置为在输出电路 通过提供LC电路的固有谐振或输出电路中的高频振荡的阻尼来减小输出电路上的开路负载,以及耦合到LCR电路的输出以检测自然谐振振荡中的一个的谐振频率检测 或高频振荡条件。 调谐谐振电路向输出滤波器后面的带有反馈的闭环D类放大器提供调制控制。