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1. 发明申请

WO2009158283A1 HYSTERETIC BUCK CONVERTER HAVING DYNAMIC THRESHOLDS 审中-公开
标题翻译：具有动态阈值的HYSTERETIC BUCK转换器
公开(公告)号：WO2009158283A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048016
申请日：2009-06-19
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L. , DING, Lei
IPC分类号： H02M3/156
CPC分类号： H02M3/1563 , H02M2001/0019 , H02M2001/0032 , Y02B70/16
摘要： A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit (K1, K2) compares the output voltage (Vout) of the buck converter to a waveform (V Low ) that is generated from an indication (+V ILOAD ) of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage (V out ) due to the increased current, preventing an excursion of the output voltage (V out ) below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold (V HIGH ) that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage (V in ) and the output voltage (V out ) waveform.
摘要翻译：迟滞降压转换器提供改进的调节控制，特别是对于降压转换器待机操作。比较电路（K1，K2）将降压转换器的输出电压（Vout）与从转换器的输出电流的指示（+ VILOAD）产生的波形（VLow）进行比较，使得导通时间的转换器随着输出电流需求的增加而提前。所产生的动作预期由于电流增加而导致的输出电压（Vout）的降低，从而防止输出电压（Vout）偏离纹波电压最小值。转换器的关断时间由限制纹波电压最大值的上阈值（VHIGH）控制。输出电流指示可以是输出电流的测量值，也可以是从输入电压（Vin）和输出电压（Vout）波形计算出的动态值。

2. 发明申请

WO2008005151A2 DIGITAL NON-INTEGER SAMPLE/HOLD IMPLEMENTED USING VIRTUAL FILTERING 审中-公开
标题翻译：使用虚拟过滤实现的数字非整数样本/保持
公开(公告)号：WO2008005151A2
公开(公告)日：2008-01-10
申请号：PCT/US2007/013608
申请日：2007-06-08
申请人： CIRRUS LOGIC, INC.
发明人： DING, Lei , MELANSON, John, L. , FEI, Xiaofan , DUEWER, Bruce
CPC分类号： H03H17/0685 , H03H17/0275 , H03H17/0614
摘要： A method and apparatus for implementing non-integer sample hold operations in a sigma-delta digital-to-analog converter system includes an interpolation filter, a polyphase filter circuit, and a modulator. The polyphase filter circuit is used to virtual upsample a digital input signal by a predetermined non-integer upsample ratio of a relatively large number. The polyphase filter circuit is formed of a long zero-order hold and a short FIR filter so that only several branches associated with the polyphase filter circuit corresponding to output samples immediately after a transition of the digital input signal is required to be calculated., thereby reducing the need to store a large number of filter coefficients and eliminating complex computations.
摘要翻译：用于在Σ-Δ数模转换器系统中实现非整数采样保持操作的方法和装置包括内插滤波器，多相滤波器电路和调制器。多相滤波器电路用于以相对较大数量的预定非整数上采样比虚拟上采样数字输入信号。多相滤波器电路由长零级保持和短FIR滤波器形成，使得仅需要计算与数字输入信号转换之后立即对应于输出采样的多相滤波器电路相关联的多个分支，由此减少了存储大量滤波器系数的需要，并消除了复杂的计算。

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