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1. 发明申请

WO2003019642A1 ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS 审中-公开
标题翻译：包含氧化有机硅烷材料的电介质材料的蚀刻工艺
公开(公告)号：WO2003019642A1
公开(公告)日：2003-03-06
申请号：PCT/US2002/026835
申请日：2002-08-22
申请人： APPLIED MATERIALS, INC.
发明人： BOITEUX, Yves, Pierre , CHEN, Hui , GREGORATTO, Ivano , HSIEH, Chang-Lin , HUNG, Hoiman , TANG, Sum-Yee, Betty
IPC分类号： H01L21/311
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31116 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L2221/1036
摘要： The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH 2 F 2 /Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016) and wider trenches. The technique is also suitable for forming dual damascene structures In additional embodiments, manufacturing systems are provided for fabricating IC structures of the present invention. These systems include a controller that is adapted for interacting with a plurality of fabricating stations.
摘要翻译：本发明提供一种用于蚀刻C掺杂氧化硅层的新颖蚀刻技术，例如部分氧化的有机硅烷材料。这种在低偏压和低至中压下使用CH2F2 / Ar化学的技术为氧化硅提供了高蚀刻选择性，并提高了对有机光致抗蚀剂的选择性。根据新技术蚀刻包括沉积在氧化硅层（1002）上的部分氧化的有机硅烷材料层（1004）的结构，形成较窄的沟槽（1010,1012,1014,1016）和更宽的沟槽。该技术也适用于形成双镶嵌结构。在另外的实施例中，提供制造系统用于制造本发明的IC结构。这些系统包括适于与多个制造站相互作用的控制器。

2. 发明申请

WO2003081645A3 AN INTEGRATED IN-SITU ETCH PROCESS PERFORMED IN A MULTICHAMBER SUBSTRATE PROCESSING SYSTEM 审中-公开
公开(公告)号：WO2003081645A3
公开(公告)日：2003-10-02
申请号：PCT/US2003/007485
申请日：2003-03-10
申请人： APPLIED MATERIALS, INC.
发明人： HSIEH, Chang-Lin , MA, Diana, Xiaobing , SHIEH, Brian, Sy Yuan , YIN, Gerald, Zheyao , SUN, Jennifer , THACH, Senh , LUO, Lee , BJORKMAN, Claes, H.
IPC分类号： H01L21/00
摘要： An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the barrier layer is etched through to the feature to be contacted in the second chamber of the multichamber substrate processing system using a process that discourages polymer formation over the relatively smooth interior surface of the second chamber. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In some embodiments the interior surface of the first chamber has a roughness between 100 and 200 Ra and in other embodiments the roughness of the first chamber's interior surface is between 110 and 160 Ra.

3. 发明申请

WO2010014399A2 CHAMBER PLASMA-CLEANING PROCESS SCHEME 审中-公开
标题翻译：室内等离子清洗工艺方案
公开(公告)号：WO2010014399A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/050686
申请日：2009-07-15
申请人： APPLIED MATERIALS, INC. , HSIEH, Chang-Lin , CHING, Chi-Hong , KOJIRI, Hidehiro , TSUI, Joshua
发明人： HSIEH, Chang-Lin , CHING, Chi-Hong , KOJIRI, Hidehiro , TSUI, Joshua
IPC分类号： H01L21/3065 , H01L21/304
CPC分类号： B08B7/0035 , H01J37/3244 , H01J37/32449 , H01J37/32862
摘要： A method for plasma-cleaning a chamber in a process tool is described. A substrate is placed on a chuck in a process chamber having a set of contaminants therein. A plasma process is executed in the process chamber to transfer the set of contaminants to the top surface of the substrate. The substrate, having the set of contaminants thereon, is removed from the process chamber.
摘要翻译：描述了用于等离子体清洁处理工具中的腔室的方法。衬底放置在其中具有一组污染物的处理室中的卡盘上。在处理室中执行等离子体处理以将污染物组转移到衬底的顶表面。将其上具有污染物集合的基板从处理室移除。

4. 发明申请

WO2007111893A2 PLASMA ETCH AND PHOTORESIST STRIP PROCESS WITH INTERVENING CHAMBER DE-FLUORINATION AND WAFER DE-FLUORINATION STEPS 审中-公开
标题翻译：等离子体蚀刻和光栅条纹工艺，具有干燥室去荧光和脱水脱氟步骤
公开(公告)号：WO2007111893A2
公开(公告)日：2007-10-04
申请号：PCT/US2007/006955
申请日：2007-03-19
申请人： APPLIED MATERIALS, INC.
发明人： ZHOU, Yifeng , DELGADINO, Gerardo, A. , HSIEH, Chang-Lin
IPC分类号： H01L21/308
CPC分类号： H01L21/31138 , H01L21/02049
摘要： A plasm etch process includes a plasma etch step performed with a photoresist mask on a workpiece using a polymerizing etch process gas that produces in the plasma polymerizing species which accumulate as a protective polymer layer on the surface of said photoresist mask during the etch step, the process including the following steps performed in the same chamber after the etch step and prior to removing the photoresist mask: (a) removing residue of the type including polymer material from chamber surfaces including a ceiling of said chamber, by coupling RF plasma source power into the chamber while coupling substantially no RF plasma bias power into the chamber, and introducing a hydrogen-containing gas into the chamber, until said residue is removed from the chamber surfaces; (b) removing the protective polymer layer from the surface of the photoresist mask, by coupling RF plasma bias power into the chamber while coupling substantially no RF plasma source power into the chamber, and introducing into the chamber a process gas comprising oxygen and carbon monoxide, until the polymer layer is removed from the surface of the photoresist mask.
摘要翻译：等离子体蚀刻工艺包括使用在蚀刻步骤期间在等离子体聚合物质中产生的聚合蚀刻工艺在光致抗蚀剂掩模的表面上积聚作为保护性聚合物层的工件上的光致抗蚀剂掩模执行的等离子体蚀刻步骤，该方法包括在蚀刻步骤之后并且在除去光致抗蚀剂掩模之前在相同的室中执行的以下步骤：（a）通过将RF等离子体源功率耦合到其中，从包括所述室的天花板的室表面去除包括聚合物材料的类型的残余物该室在基本上不将RF等离子体偏压功率耦合到室中，并且将含氢气体引入室中，直到从室表面除去所述残余物; （b）通过将RF等离子体偏压功率耦合到腔室中，同时将基本上没有RF等离子体源功率耦合到腔室中，从而保护聚合物层从光致抗蚀剂掩模的表面上除去，并且将包含氧和一氧化碳的工艺气体直到聚合物层从光致抗蚀剂掩模的表面去除。

5. 发明申请

WO2004038792A2 BARC SHAPING FOR IMPROVED FABRICATION OF DUAL DAMASCENE INTEGRATED CIRCUIT FEATURES 审中-公开
标题翻译：用于改进双金属板集成电路特性的BARC形状
公开(公告)号：WO2004038792A2
公开(公告)日：2004-05-06
申请号：PCT/US2003/031824
申请日：2003-10-09
申请人： APPLIED MATERIALS, INC.
发明人： HSIEH, Chang-Lin , ZHANG, QiQun , YUAN, Jie , LEUNG, Terry , HALIM, Silvia
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating ("BARC") is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by "fencing" material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARCplug, 107, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating. A directional anisotropic etching of BARC, and more particularly, an ammonia plasma etch, is one convenient method of removing BARC and forming the desired convex upper surface.
摘要翻译：描述了用于制造集成电路中的双镶嵌特征的方法，材料和结构。在经由第一双镶嵌制造中，通常将底部抗反射涂层（“BARC”）沉积到通孔107周围的通孔和场区域中。随后的使用常规蚀刻化学物质的沟槽蚀刻通常导致BARC的隔离区域， 107a，被“围栏”包围。材料108位于通孔的底部。这种栅栏阻碍了具有阻挡层/粘附层的保形涂层，并且可能降低器件产量。本发明涉及在刻蚀沟槽之前形成BARCplug 107，其部分填充通孔并具有凸起的上表面400。显示这种BARC结构会导致刻蚀而不形成栅栏和干净的双镶嵌结构用于随后的涂覆。 BARC的定向各向异性刻蚀，更具体地说，氨等离子体刻蚀是去除BARC并形成所需的凸面上表面的一种方便的方法。

6. 发明申请

WO2003050863A1 PROCESS FOR SELECTIVELY ETCHING DIELECTRIC LAYERS 审中-公开
标题翻译：选择蚀刻电介质层的工艺
公开(公告)号：WO2003050863A1
公开(公告)日：2003-06-19
申请号：PCT/US2002/038862
申请日：2002-12-05
申请人： APPLIED MATERIALS, INC.
发明人： HSIEH, Chang-Lin , YUAN, Jie , CHEN, Hui , PANAGOPOULOS, Theodoros , YE, Yan
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/31629 , H01L21/31633 , H01L21/76808 , H01L21/76835
摘要： A method is provided for etching a dielectric structure. The dielectric structure comprises: (a) a layer of undoped silicon oxide or F-doped silicon oxide; and (b) a layer of C,H-doped silicon oxide. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. As one example, the plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF 3 ). As another example, the plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N 2 ) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF 4 ). In this etching step, the layer of C,H-doped silicon oxide is preferentially etched relative to the layer of undoped silicon oxide or F-doped silicon oxide. The method of the present invention is applicable, for example, to dual damascene structures.
摘要翻译：提供了蚀刻电介质结构的方法。电介质结构包括：（a）一层未掺杂的氧化硅或掺杂F的氧化硅; 和（b）C，H掺杂的氧化硅层。在等离子体蚀刻步骤中蚀刻电介质结构，使用包含氮原子和氟原子的等离子体源气体进行等离子体蚀刻步骤。作为一个示例，等离子体源气体可以包括包含一个或多个氮原子和一个或多个氟原子（例如NF 3）的气态物质。作为另一示例，等离子体源气体可以包括（a）包含一个或多个氮原子（例如，N 2）的气态物质和（b）包含一个或多个氟原子的气态物质（例如，碳氟化合物气体例如 CF4）。在该蚀刻步骤中，相对于未掺杂的氧化硅层或掺杂F的氧化硅层优先蚀刻C，H掺杂的氧化硅层。本发明的方法例如可应用于双镶嵌结构。

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