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1. 发明申请

WO2018038829A1 SYSTEMS AND METHODS FOR AUTHENTICATING FIRMWARE STORED ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于验证存储在集成电路中的固件的系统和方法
公开(公告)号：WO2018038829A1
公开(公告)日：2018-03-01
申请号：PCT/US2017/043084
申请日：2017-07-20
申请人： ALTERA CORPORATION
发明人： PEDERSEN, Bruce, B.
IPC分类号： G06F21/78 , G06F21/76 , H04L9/32 , G06F21/60
CPC分类号： G06F21/44 , G06F21/562 , G06F21/572 , G06F21/72 , G06F21/76 , G06F2221/033 , H04L9/0869 , H04L9/3242 , H04L9/3247 , H04L2209/08
摘要： The invention discloses a method of authenticating data stored in an integrated circuit. The method includes storing randomized data in the integrated circuit such that the randomized data occupies each address space of the memory circuit that is not occupied by the stored data. The method also includes generating a first digital signature using the integrated circuit in response to authenticating a concatenation of the stored data and the first copy of randomized data. The method further includes generating a second digital signature in response to authenticating concatenation of a manufacturer-provided copy of the stored data and the second copy of randomized data using a computer- implemented authentication application and authenticating the data stored in the integrated circuit according to whether the first signature matches the second signature.
摘要翻译：本发明公开了一种对存储在集成电路中的数据进行认证的方法。该方法包括将随机化数据存储在集成电路中，使得随机化数据占据存储器电路未被存储数据占用的每个地址空间。该方法还包括响应于认证所存储的数据和随机化数据的第一副本的串联使用集成电路来生成第一数字签名。该方法进一步包括响应于使用计算机实现的认证应用认证制造商提供的存储数据副本和随机化数据的第二副本的级联并且根据是否存储在集成电路中的数据认证来产生第二数字签名第一个签名与第二个签名匹配。

2. 发明申请

WO2012148707A2 SYSTEMS AND METHODS FOR DETECTING AND MITIGATING PROGRAMMABLE LOGIC DEVICE TAMPERING 审中-公开
标题翻译：用于检测和缓解可编程逻辑器件篡改的系统和方法
公开(公告)号：WO2012148707A2
公开(公告)日：2012-11-01
申请号：PCT/US2012/033481
申请日：2012-04-13
申请人： ALTERA CORPORATION , PEDERSEN, Bruce, B.
发明人： PEDERSEN, Bruce, B.
IPC分类号： H03K19/007 , G11C7/24
CPC分类号： G06F21/86 , G06F21/76 , H03K19/17768
摘要： Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
摘要翻译：公开了用于防止篡改可编程集成电路器件的系统和方法。通常，可编程器件（如FPGA）具有两个操作阶段; 配置阶段和用户模式阶段。为了防止可编程设备的篡改和/或逆向工程，可以在操作的任一阶段期间采用各种防篡改技术以在怀疑篡改后禁用设备和/或擦除存储在设备上的敏感信息。一种类型的篡改涉及用许多错误的配置尝试轰击设备以解密加密的数据。通过利用脏位和粘性错误计数器，设备可以跟踪已经发生的失败配置尝试的次数，并且当在设备仍处于配置操作阶段时怀疑被篡改时启动防篡改操作。 p>

3. 发明申请

WO2012148743A2 SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY SYSTEMS 审中-公开
标题翻译：用于防止记忆系统中的数据存在的系统和方法
公开(公告)号：WO2012148743A2
公开(公告)日：2012-11-01
申请号：PCT/US2012/033997
申请日：2012-04-18
申请人： ALTERA CORPORATION , PEDERSEN, Bruce, B. , REESE, Dirk, A.
发明人： PEDERSEN, Bruce, B. , REESE, Dirk, A.
IPC分类号： G11C7/10 , G11C7/20 , G11C11/41
CPC分类号： G06F21/79 , G06F21/76 , G11C7/20 , G11C11/419
摘要： Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.
摘要翻译：提供了用于防止存储器系统中的数据剩余的方法，电路和系统。原始数据存储在第一存储器中，其可以是静态随机存取存储器（SRAM）。数据另外存储在第二个存储器中。周期性地反转第一存储器中的数据，从而防止第一存储器中的数据剩余。第二存储器中的数据与第一存储器中的数据周期性地反转。第二存储器中的数据用于跟踪第一存储器中的数据的反转状态。第一存储器中的原始数据可被重构，执行第一存储器中的数据和第二存储器中的数据之间的逻辑异或运算。

4. 发明申请

WO2012148658A3 SYSTEMS AND METHODS FOR PROVIDING USER-INITIATED LATCH-UP TO DESTROY SRAM DATA 审中-公开
公开(公告)号：WO2012148658A3
公开(公告)日：2012-11-01
申请号：PCT/US2012/032858
申请日：2012-04-10
申请人： ALTERA CORPORATION , REESE, Dirk, A. , PEDERSEN, Bruce, B.
发明人： REESE, Dirk, A. , PEDERSEN, Bruce, B.
IPC分类号： H03K19/007 , G11C7/24
摘要： Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.

5. 发明申请

WO2010107515A1 VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY 审中-公开
标题翻译：具有软错误UPS易失性的易失性存储器元件
公开(公告)号：WO2010107515A1
公开(公告)日：2010-09-23
申请号：PCT/US2010/021352
申请日：2010-01-19
申请人： ALTERA CORPORATION , PEDERSEN, Bruce, B.
发明人： PEDERSEN, Bruce, B.
IPC分类号： G11C7/00 , G11C11/40 , G11C7/24
CPC分类号： G11C11/412 , G11C7/20 , G11C11/4125 , H03K19/00392 , H03K19/177 , H03K19/1776 , H03K19/17764
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.
摘要翻译：提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

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