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1. 发明申请

WO2009032230A3 A CMOS DEVICE HAVING GATE INSULATION LAYERS OF DIFFERENT TYPE AND THICKNESS AND METHOD OF FORMING THE SAME 审中-公开
公开(公告)号：WO2009032230A3
公开(公告)日：2009-03-12
申请号：PCT/US2008/010299
申请日：2008-08-30
申请人： ADVANCED MICRO DEVICES, INC. , WEI, Andy , WAITE, Andrew , TRENTZSCH, Martin , GROSCHOPF, Johannes , GRASSHOFF, Gunter , OTT, Andreas
发明人： WEI, Andy , WAITE, Andrew , TRENTZSCH, Martin , GROSCHOPF, Johannes , GRASSHOFF, Gunter , OTT, Andreas
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： In the process sequence for replacing conventional gate electrode structures (310) by high-k metal gate structures (310N, 310B, 310P), the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps (322, 325, 327, 331), thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain- inducing mechanisms in the transistor level as well as in the contact level.

2. 发明申请

WO2009108366A2 A SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含降低高度的金属栅极堆叠的半导体器件及其形成方法
公开(公告)号：WO2009108366A2
公开(公告)日：2009-09-03
申请号：PCT/US2009/001283
申请日：2009-02-27
申请人： ADVANCED MICRO DEVICES, INC. , BEYER, Sven , STEPHAN, Rolf , TRENTZSCH, Martin , PRESS, Patrick
发明人： BEYER, Sven , STEPHAN, Rolf , TRENTZSCH, Martin , PRESS, Patrick
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7843 , H01L29/7848
摘要： By providing a CMP stop layer in a metal gate stack (160), the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas (152), thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material (161) may be positioned more closely to the channel region substantially without deteriorating gate conductivity.
摘要翻译：通过在金属栅极堆叠（160）中设置CMP停止层，在深层漏极和源极区域（152）的定义之后，其初始高度可被有效地降低，从而为形成高应力电介质材料提供了增强的工艺条件。因此，电介质材料（161）可以基本上不更改栅极导电性而更靠近沟道区。

3. 发明申请

WO2011025804A1 WORK FUNCTION ADJUSTMENT IN HIGH-K GATES STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS 审中-公开
标题翻译：包括不同厚度的门电介质的高K栅格堆栈中的工作功能调整
公开(公告)号：WO2011025804A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046572
申请日：2010-08-25
申请人： GLOBALFOUNDRIES INC. , SCHEIPER, Thilo , WEI, Andy , TRENTZSCH, Martin
发明人： SCHEIPER, Thilo , WEI, Andy , TRENTZSCH, Martin
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823462 , H01L21/823857
摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species (254A) within the high-k dielectric material (253) with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species (254A), the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures (250A, 250B) may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors (260A, 260B) having a different thickness gate dielectric material may be avoided.
摘要翻译：在复杂的制造技术中，通过在高k电介质材料（253）内提供基本上相同的空间分布的功能调节物质（254A）的功函数，可以在早期制造阶段调整工作功能和晶体管元件的阈值电压在不同厚度的栅极电介质材料中。在加入功函数调整物质（254A）之后，可以通过选择性地形成额外的电介质层来调节栅介电材料的最终厚度，使得栅电极结构（250A，250B）的进一步构图可以用与常规制造技术的高度兼容性。因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管（260A，260B）的阈值电压的非常复杂的过程。

4. 发明申请

WO2011008401A1 UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING 审中-公开
标题翻译：通过在门控图案之前扩散金属物种调节放大晶体管的阈值电压来均质高K金属栅极堆叠
公开(公告)号：WO2011008401A1
公开(公告)日：2011-01-20
申请号：PCT/US2010/038923
申请日：2010-06-17
申请人： GLOBALFOUNDRIES INC. , CARTER, Richard , GRAETSCH, Falk , TRENTZSCH, Martin , BEYER, Sven , REIMER, Berthold , BINDER, Robert , BAYAH, Boris
发明人： CARTER, Richard , GRAETSCH, Falk , TRENTZSCH, Martin , BEYER, Sven , REIMER, Berthold , BINDER, Robert , BAYAH, Boris
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L21/8238
CPC分类号： H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.
摘要翻译：在基本上相同的结构的基础上对用于N沟道晶体管和P沟道晶体管的复杂的栅电极结构（235A，235B）进行构图，然而，可以在早期制造阶段中完成功函数调整。为此，在将期望的功函数金属物质并入高k介电材料（212）中之后，去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

5. 发明申请

WO2010132319A1 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 审中-公开
标题翻译：通过扩大栅极电介质层材料来调节电介质稳定电容的电压电压调节电压
公开(公告)号：WO2010132319A1
公开(公告)日：2010-11-18
申请号：PCT/US2010/034164
申请日：2010-05-10
申请人： GLOBAL FOUNDRIES INC. , CARTER, Richard , TRENTZSCH, Martin , BEYER, Sven , PAL, Rohit
发明人： CARTER, Richard , TRENTZSCH, Martin , BEYER, Sven , PAL, Rohit
IPC分类号： H01L21/8234 , H01L21/3115 , H01L21/28 , H01L29/51
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer (121) including a desired species that may diffuse into the gate dielectric material (110) prior to performing a treatment for stabilizing the sensitive gate dielectric material (110). In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在执行用于稳定敏感栅极电介质材料（110）的处理之前提供包括可扩散到栅极电介质材料（110）中的所需物质的覆盖层（121）来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

6. 发明申请

WO2010132319A8 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 审中-公开
公开(公告)号：WO2010132319A8
公开(公告)日：2010-11-18
申请号：PCT/US2010/034164
申请日：2010-05-10
申请人： GLOBAL FOUNDRIES INC. , CARTER, Richard , TRENTZSCH, Martin , BEYER, Sven , PAL, Rohit
发明人： CARTER, Richard , TRENTZSCH, Martin , BEYER, Sven , PAL, Rohit
IPC分类号： H01L21/8234 , H01L21/3115 , H01L21/28 , H01L29/51
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer (121) including a desired species that may diffuse into the gate dielectric material (110) prior to performing a treatment for stabilizing the sensitive gate dielectric material (110). In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

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