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1. 发明申请

WO2005048320A3 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FORM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 审中-公开
公开(公告)号：WO2005048320A3
公开(公告)日：2005-05-26
申请号：PCT/US2004/028486
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , ZHONG, Huicai , GOO, Jung-Suk , HOLBROOK, Allison, Kay , JEON, Joong, S. , KLUTH, George, Jonathan
发明人： XIANG, Qi , ZHONG, Huicai , GOO, Jung-Suk , HOLBROOK, Allison, Kay , JEON, Joong, S. , KLUTH, George, Jonathan
IPC分类号： H01L21/8238
摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).

2. 发明申请

WO2005020323A2 FIELD EFFECT TRANSISTOR HAVING INCREASED CARRIER MOBILITY 审中-公开
标题翻译：具有增加载波移动性的场效应晶体管
公开(公告)号：WO2005020323A2
公开(公告)日：2005-03-03
申请号：PCT/US2004/025565
申请日：2004-08-05
申请人： ADVANCED MICRO DEVICES, INC. , ANG, Boon-Yong , XIANG, Qi , GOO, Jung-Suk
发明人： XIANG, Qi , GOO, Jung-Suk
IPC分类号： H01L27/00
CPC分类号： H01L29/4983 , H01L29/02 , H01L29/4925 , H01L29/513 , H01L29/78 , H01L29/7845 , Y10S438/938
摘要： According to one exemplary embodiment, a FET which is situated over a substrate (104), comprises a channel (112) situated in the substrate (104). The FET further comprises a first gate dielectric (116) situated over the channel (112), where the first gate dielectric (116) has a first coefficient of thermal expansion. The FET further comprises a first gate electrode (114) situated over the first gate dielectric (116), where the first gate electrode (114) has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel (112).
摘要翻译：根据一个示例性实施例，位于衬底（104）上方的FET包括位于衬底（104）中的通道（112）。 FET还包括位于通道（112）上方的第一栅极电介质（116），其中第一栅极电介质（116）具有第一热膨胀系数。 FET还包括位于第一栅极电介质（116）上方的第一栅电极（114），其中第一栅电极（114）具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一栅电极热膨胀系数，从而导致FET中载流子迁移率的增加。例如，第二热膨胀系数可以大于第一热膨胀系数。载流子迁移率的增加可以由例如在通道（112）中产生的拉伸应变引起。

3. 发明申请

WO2004032246A1 FINFET HAVING IMPROVED CARRIER MOBILITY AND METHOD OF ITS FORMATION 审中-公开
标题翻译：具有改进载体移动性的FINFET及其形成方法
公开(公告)号：WO2004032246A1
公开(公告)日：2004-04-15
申请号：PCT/US2003/028660
申请日：2003-09-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LIN, Ming-Ren , GOO, Jung-Suk , WANG, Haihong , XIANG, Qi
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L29/78687
摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body (46) is patterned from a layer of silicon germanium (SiGe) (42) that overlies a dielectric layer (40). An epitaxial layer of silicon (34) is then formed on the silicon germanium FinFET body (46). A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
摘要翻译： FinFET器件采用应变硅来增强载流子迁移率。在一种方法中，FinFET体（46）从覆盖在电介质层（40）上的硅锗层（SiGe）（42）构图。然后在硅锗FinFET体（46）上形成硅（34）的外延层。由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

4. 发明申请

WO2005071738A2 SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE 审中-公开
标题翻译： SHOWOW TRENCH隔离过程和结构
公开(公告)号：WO2005071738A2
公开(公告)日：2005-08-04
申请号：PCT/US2004/043107
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
发明人： XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
IPC分类号： H01L21/762
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material (36) is formed after the trench (34) is formed. The process can be utilized on a compound semiconductor layer (15) above a buried oxide (Box) layer (14).
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽（34）之后形成应变材料（36）。该方法可以用在掩埋氧化物（Box）层（14）上方的化合物半导体层（15）上。

5. 发明申请

WO2005071728A1 METHOD OF FABRICATING A STRAINED FINFET CHANNEL 审中-公开
标题翻译：制造应变FINFET通道的方法
公开(公告)号：WO2005071728A1
公开(公告)日：2005-08-04
申请号：PCT/US2004/043106
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
发明人： XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842
摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer (140) above an insulating layer (130), providing a trench (142) in the compound semiconductor layer (140), and providing a strained semiconductor layer (144) above the compound semiconductor layer (140) and within the trench (142). The method can also include removing the strained semiconductor layer (144) from above the compound semiconductor layer (140), thereby leaving the strained semiconductor layer (144) within the trench (142) and removing the compound semiconductor layer (140) to leave the strained semiconductor layer (144) and form the fin-shaped channel region (152).
摘要翻译：示例性实施例涉及FinFET沟道结构形成的方法。该方法可以包括在绝缘层（130）之上提供化合物半导体层（140），在化合物半导体层（140）中提供沟槽（142），并且在化合物半导体层上方提供应变半导体层（144） 140）并且在沟槽（142）内。该方法还可以包括从化合物半导体层（140）上方去除应变半导体层（144），从而将应变半导体层（144）留在沟槽（142）内，并去除化合物半导体层（140）以离开应变半导体层（144）并形成鳍状沟道区域（152）。

6. 发明申请

WO2004061920A3 METHOD OF FORMING A THICK STRAINED SILICON LAYER AND SEMICONDUCTOR STRUCTURES INCORPORATING A THICK STRAINED SILICON LAYER 审中-公开
公开(公告)号：WO2004061920A3
公开(公告)日：2004-07-22
申请号：PCT/US2003/034673
申请日：2003-10-30
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WANG, Haihong , BESSER, Paul, R. , GOO, Jung-Suk , NGO, Minh, Van , PATON, Eric, N. , XIANG, Qi
IPC分类号： H01L21/20
摘要： A strained silicon layer (50) s grown on a layer of silicon germanium (40) and a layer of silicon germanium (52) is grown on the strained silicon (50) in a single continuous in situ deposition process with the strained silicon (50). Shallow trench isolations (48) are formed in the lower layer of silicon germanium (40) prior to formation of the strained silicon layer (50). The two silicon germanium layers (40, 52) effectively provide dual substrates at both surfaces of the strained silicon layer (50) that serve to maintain the tensile strain of the strained silicon layer (50) and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon (50) that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers (40, 52). The formation of shallow trench isolations (48) prior to formation of the strained silicon layer (50) avoids subjecting the strained silicon (50) layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

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