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1. 发明申请

WO2017052621A1 MEMORY CELL WITH ASYMMETRIC CONDUCTION TO REDUCE WRITE MINIMUM OPERATING VOLTAGE (WVMIN) AND POWER CONSUMPTION 审中-公开
标题翻译：具有不对称导通的存储器单元以减少写入最小工作电压（WVMIN）和功耗
公开(公告)号：WO2017052621A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052352
申请日：2015-09-25
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C7/02 , G11C11/412 , G11C11/419
摘要： Techniques for providing asymmetric conduction within an SRAM bit cell are provided and may substantially reduce energy consumption during write operations, and may also reduce the write minimum operation voltage (WVmin) for an SRAM device. In particular, some aspects disclosed herein include modifying or otherwise providing pull-up transistors configured to asymmetrically conduct to prevent current flow in a reverse direction, and more particularly, to prevent or otherwise mitigate current flowing back to Vcc during write operations. This can reduce voltage swings that would otherwise occur as internal bit cell nodes Q/Q# discharge, and thus, may reduce overall power consumption. The asymmetrical conducting characteristics may further reduce the magnitude of disturb currents within unselected cells (e.g., cells not selected for writes) and thus prevent the loss of data through inadvertent writes.
摘要翻译：提供了用于在SRAM位单元内提供不对称传导的技术，并且可以显着降低写入操作期间的能量消耗，并且还可以降低SRAM器件的写入最小工作电压（WVmin）。特别地，本文公开的一些方面包括修改或以其他方式提供被配置为不对称地导通的上拉晶体管，以防止在相反方向上的电流流动，更具体地，涉及防止或以其它方式缓解在写入操作期间流向Vcc的电流。这可以减少当内部位单元节点Q / Q＃放电时会发生的电压摆幅，从而可能降低总功耗。不对称导电特性可以进一步减小未选择的单元（例如，未被选择用于写入的单元）内的干扰电流的大小，从而通过无意写入来防止数据丢失。

2. 发明申请

WO2016105436A1 SPIN-ORBIT LOGIC WITH CHARGE INTERCONNECTS AND MAGNETOELECTRIC NODES 审中-公开
标题翻译：具有电荷互连和磁电效应的旋转逻辑
公开(公告)号：WO2016105436A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072447
申请日：2014-12-26
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02
CPC分类号： H01L27/22 , H01L27/228 , H01L43/08 , H03K19/173 , H03K19/18
摘要： An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.
摘要翻译：一种包括旋转电荷转换节点的装置; 以及对自旋转换节点的电荷，其中到自旋电荷转换节点的输入在电荷到自旋转换节点处产生输出。一种包括包括输入节点和输出节点的磁体的装置，所述输入节点包括可操作以在所述磁体中产生磁响应的电容器，所述输出节点包括至少一个自旋电荷转换材料。一种包括从第一磁体注入自旋电流的方法; 将自旋电流转换成可操作以产生与第二磁体的磁电相互作用的充电电流; 以及响应于所述磁电相互作用而改变所述第二磁体的磁化方向。一种包括从磁体的输入节点注入自旋电流的方法; 以及将所述自旋电流转换为所述磁体的输出节点处的充电电流。

3. 发明申请

WO2014204492A1 MTJ SPIN HALL MRAM BIT-CELL AND ARRAY 审中-公开
标题翻译： MTJ旋转磁带MRAM位电池和阵列
公开(公告)号：WO2014204492A1
公开(公告)日：2014-12-24
申请号：PCT/US2013/047153
申请日：2013-06-21
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： G11C11/15 , H01L27/115 , H01L21/8247
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/18 , H01L27/226 , H01L27/228 , H01L43/06 , H01L43/08 , H01L43/12
摘要： Described is an apparatus 1T-1 Magnetic Tunnel Junction (MTJ) Spin Hall Magnetic Random Access Memory (MRAM) bit-cell and array, and method of forming such. The apparatus comprises: a select line; an interconnect with Spin Hall Effect (SHE) material, the interconnect coupled to a write bit line; a transistor coupled to the select line and the interconnect, the transistor controllable by a word line; and a MTJ device having a free magnetic layer coupled to the interconnect.
摘要翻译：描述了一种装置1T-1磁隧道结（MTJ）旋转磁体随机存取存储器（MRAM）位单元和阵列及其形成方法。该装置包括：选择线; 与旋转霍尔效应（SHE）材料的互连，耦合到写位线的互连; 耦合到选择线和互连的晶体管，晶体管可由字线控制; 以及具有耦合到互连的自由磁性层的MTJ装置。

4. 发明申请

WO2012134570A1 THREE-DIMENSIONAL MAGNETIC CIRCUITS INCLUDING MAGNETIC CONNECTORS 审中-公开
标题翻译：包括磁连接器在内的三维磁电路
公开(公告)号：WO2012134570A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/066791
申请日：2011-12-22
申请人： INTEL CORPORATION , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/22 , H01L43/08
摘要： A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.
摘要翻译：包括至少两个自旋电子装置的装置及其制造方法。磁性连接器在两个自旋电子器件之间延伸以在两者之间进行磁化。磁连接器可进一步设置成传导电流以切换两个自旋电子器件之一的磁化。

5. 发明申请

WO2019066875A1 FIELD EFFECT TRANSISTORS HAVING FERROELECTRIC OR ANTIFERROELECTRIC GATE DIELECTRIC STRUCTURE 审中-公开
公开(公告)号：WO2019066875A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054164
申请日：2017-09-28
申请人： INTEL CORPORATION , KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
发明人： KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51
摘要： Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

6. 发明申请

WO2015147849A1 TUNNELING FIELD EFFECT TRANSISTORS WITH A VARIABLE BANDGAP CHANNEL 审中-公开
标题翻译：具有可变带宽通道的隧道场效应晶体管
公开(公告)号：WO2015147849A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032117
申请日：2014-03-28
申请人： INTEL CORPORATION , AVCI, Uygar E. , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： AVCI, Uygar E. , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , H01L25/16 , H01L29/0847 , H01L29/1025 , H01L29/1054 , H01L29/24 , H01L29/42384 , H01L29/42392 , H01L29/66356 , H01L29/66969 , H01L29/7391 , H01L29/78648 , H01L49/003
摘要： Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.
摘要翻译：描述包括可变带隙通道的隧穿场效应晶体管（TFET）。在一些实施例中，可变带隙通道的一个或多个带隙特性可以通过施加或取出诸如电压或电场的力中的至少一个来动态改变。在一些实施例中，可变带隙通道可以被配置成响应于施加和/或撤回力而从接通到关闭状态和反之亦然。可变带隙通道可以表现出在ON状态下比在OFF状态下更小的带隙。结果，TFET可以呈现出一个或多个相对较高的导通电流，相对低的截止电流以及低于60mV /十倍的次阈值摆幅。

7. 发明申请

WO2016048317A1 STRAIN ASSISTED SPIN TORQUE SWITCHING SPIN TRANSFER TORQUE MEMORY 审中-公开
标题翻译：应变辅助转子扭矩开关转子转子转子记忆
公开(公告)号：WO2016048317A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057356
申请日：2014-09-25
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , KHAN, Asif , KIM, Raseong , GHANI, Tahir , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , KHAN, Asif , KIM, Raseong , GHANI, Tahir , YOUNG, Ian A.
IPC分类号： G11C11/15
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L27/20 , H01L41/20 , H01L43/02 , H01L43/08 , H01L43/10
摘要： Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
摘要翻译：描述了一种装置，其包括：具有自由磁性层的磁性隧道结（MTJ）; 压电层; 以及耦合到自由磁性层和压电层的导电应变传递层。描述了一种方法，其包括：用电压驱动的电容性刺激激发压电层; 并通过应变辅助层写入耦合到压电层的MTJ。还描述了一种装置，包括：晶体管; 耦合到所述晶体管的导电应变传递层; 以及具有耦合到导电应变传输层的自由磁性层的MTJ器件。

8. 发明申请

WO2016007135A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
标题翻译：基于负面差分电阻的记忆
公开(公告)号：WO2016007135A1
公开(公告)日：2016-01-14
申请号：PCT/US2014/045695
申请日：2014-07-08
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.
摘要翻译：描述了一种存储位单元，包括：存储节点; 耦合到存储节点的存取晶体管; 电容器，其具有耦合到所述存储节点的第一端子; 以及耦合到存储节点的一个或多个负差分电阻器件，使得存储位单元不具有接地线或供电线之一或两者。

9. 发明申请

WO2015099703A1 HYBRID MEMORY AND MTJ BASED MRAM BIT-CELL AND ARRAY 审中-公开
标题翻译：混合存储器和基于MTJ的MRAM位单元和阵列
公开(公告)号：WO2015099703A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077668
申请日：2013-12-24
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , YOUNG, Ian A.
IPC分类号： G11C11/15
CPC分类号： G11C14/0036 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C14/0018 , G11C14/0045 , H01L27/10832 , H01L27/1087 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12 , H04L9/0897
摘要： Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.
摘要翻译：描述了一种用于混合eDRAM和MRAM存储器单元的装置，包括：具有第一端子和第二端子的电容器; 第一晶体管，其具有耦合到第一字线（WL）的栅极端子，耦合到位线（BL）的源极/漏极端子以及耦合到所述电容器的所述第一端子的漏极/源极端子; 具有第一端子和第二端子的电阻性存储元件，所述电阻式存储元件器件的所述第一端子耦合到所述电容器的第一端子; 以及第二晶体管，其具有耦合到第二WL的栅极端子，耦合到源极线（SL）的源极/漏极端子以及耦合到所述电阻性存储器件器件的所述第二端子的漏极/源极端子。

10. 发明申请

WO2014142910A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 审中-公开
标题翻译：基于纳米级的机械切换装置
公开(公告)号：WO2014142910A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/031607
申请日：2013-03-14
申请人： INTEL CORPORATION , PAWASHE, Chytra , KIM, Raseong , KIM, Seiyon , KUHN, Kelin J. , MANIPATRUNI, Sasikanth , RIOS, Rafael , YOUNG, Ian A. , LIN, Kevin , CHAUDHRY, Anurag
发明人： PAWASHE, Chytra , KIM, Raseong , KIM, Seiyon , KUHN, Kelin J. , MANIPATRUNI, Sasikanth , RIOS, Rafael , YOUNG, Ian A. , LIN, Kevin , CHAUDHRY, Anurag
IPC分类号： H01L29/00 , B81B7/00
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括设置在设置在基板上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线间隔开。

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