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1. 发明申请

WO2006063337A2 DMA LATENCY COMPENSATION WITH SCALING LINE BUFFER 审中-公开
标题翻译： DMA延迟补偿与缩放线缓冲区
公开(公告)号：WO2006063337A2
公开(公告)日：2006-06-15
申请号：PCT/US2005/044885
申请日：2005-12-09
申请人： WIS TECHNOLOGIES, INC. , SHA, Li , HUANG, Qifan
发明人： SHA, Li , HUANG, Qifan
IPC分类号： G09G5/36
CPC分类号： G09G5/395 , G09G5/391
摘要： A video processing system configured with DMA latency compensation is disclosed. This compensation helps minimize or otherwise mitigate shortages of data to the display, thereby improving the quality of displayed video. A relatively small line buffer is used to stage data for video processing. Should an underflow of data occur (where the buffer reading process is ahead of the buffer writing process), data is read from the previous line buffer. This not only prevents shortages of data to the display, but also provides data that is more likely to be relevant to the actual scene being displayed (as compared to random data).
摘要翻译：公开了配置有DMA等待时间补偿的视频处理系统。该补偿有助于最小化或以其他方式减少数据到显示器的短缺，从而提高显示视频的质量。使用相对小的行缓冲器来进行视频处理的数据。如果数据发生下溢（缓冲区读取过程在缓冲区写入过程之前），则从前一行缓冲区读取数据。这不仅可以防止显示数据的短缺，而且可以提供更可能与正在显示的实际场景相关的数据（与随机数据相比）。

2. 发明申请

WO2005112434A3 NOISE FILTER FOR VIDEO PROCESSING 审中-公开
标题翻译：用于视频处理的噪声滤波器
公开(公告)号：WO2005112434A3
公开(公告)日：2007-09-27
申请号：PCT/US2005015402
申请日：2005-05-03
申请人： WIS TECHNOLOGIES INC , ZENG WEIMIN , SHA LI , ZHU PING
发明人： ZENG WEIMIN , SHA LI , ZHU PING
IPC分类号： G06K9/40 , H04N5/21 , H04N7/12 , H04N7/26 , H04N11/02
CPC分类号： H04N5/21 , H04N19/117 , H04N19/14
摘要： A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.
摘要翻译：用于视频处理系统的噪声滤波器包括块选择器，成本计算器，成本表，成本比较器和系数滤波器。块选择器被耦合以从量化单元接收数据并且选择用于额外滤波的块。所选择的块被提供给成本计算器使用成本表确定块中的每个系数的成本，并且将成本相加。成本比较器将总和比较为阈值，并且如果总数大于预设阈值，则使用系数滤波器对系数进行滤波。然后，VLC单元的噪声滤波器输出滤波器数据。

3. 发明申请

WO2006063260A3 DIGITAL SIGNAL PROCESSING STRUCTURE FOR DECODING MULTIPLE VIDEO STANDARDS 审中-公开
标题翻译：用于解码多个视频标准的数字信号处理结构
公开(公告)号：WO2006063260A3
公开(公告)日：2007-06-21
申请号：PCT/US2005044683
申请日：2005-12-09
申请人： WIS TECHNOLOGIES INC , LIN TENG CHIANG , YUAN HONGJUN , ZENG WEIMIN , PENG LIANG
发明人： LIN TENG CHIANG , YUAN HONGJUN , ZENG WEIMIN , PENG LIANG
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/436 , H04N19/12 , H04N19/136 , H04N19/172 , H04N19/423 , H04N19/44 , H04N19/61
摘要： A DSP structure (Fig. 1) capable of processing both an H.264 decoding flow and a non-H.264 decoding flow. The non-H.264 decoding flow can be used for standards such as MPEG 1/2/4, H.263, WMV9 and Sony Digital video. The DSP structure including: a dequantizer (DEQ), a row IDCT (IDCTR), a column IDCT (IDCTC), and a motion compensation unit(DeMC).
摘要翻译：能够处理H.264解码流和非H.264解码流的DSP结构（图1）。非H.264解码流可用于MPEG 1/2/4，H.263，WMV9和Sony Digital视频等标准。 DSP结构包括：去量化器（DEQ），行IDCT（IDCTR），列IDCT（IDCTC）和运动补偿单元（DeMC）。

4. 发明申请

WO2006063343A3 SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING 审中-公开
标题翻译：用于运动矢量预测和残留解码的共享管道结构
公开(公告)号：WO2006063343A3
公开(公告)日：2007-05-24
申请号：PCT/US2005044892
申请日：2005-12-09
申请人： WIS TECHNOLOGIES INC , LIN TENG CHIANG , ZENG WEIMIN
发明人： LIN TENG CHIANG , ZENG WEIMIN
IPC分类号： H04N7/12
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

5. 发明申请

WO2005032114A2 SYSTEM AND METHOD FOR EFFICIENTLY PERFORMING AN INVERSE TELECINE PROCEDURE 审中-公开
标题翻译：有效地执行反向电子化程序的系统和方法
公开(公告)号：WO2005032114A2
公开(公告)日：2005-04-07
申请号：PCT/US2004031277
申请日：2004-09-23
申请人： WIS TECHNOLOGIES INC , YUAN HONGJUN , QU SHENG , MEYER DANIEL W
发明人： YUAN HONGJUN , QU SHENG , MEYER DANIEL W
IPC分类号： H04N20060101 , H04N7/01 , H04N
CPC分类号： H04N7/0112
摘要： A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.
摘要翻译：用于有效地执行逆电视电影过程的系统和方法包括逆电视电影模块，其通过对输入帧应用反向电视电影策略将视频信息的输入帧转换成相应的输出帧。然后，运动统计发生器计算与输出帧相对应的运动统计结果。同步器模块然后将运动统计结果与同步表中的条目进行比较，以确定反向电视电影过程是否正确同步。然后，当反向电视电影过程未正确同步时，同步器模块可以重新定位逆电视电影过程的当前起始边界。

6. 发明申请

WO2007064341A3 COMBINED SCALING, FILTERING, AND SCAN CONVERSION 审中-公开
标题翻译：组合缩放，过滤和扫描转换
公开(公告)号：WO2007064341A3
公开(公告)日：2009-04-16
申请号：PCT/US2005044685
申请日：2005-12-09
申请人： WIS TECHNOLOGIES INC , HUANG QIFAN , TIAN YU T
发明人： HUANG QIFAN , TIAN YU T
IPC分类号： H04N7/01 , G06F17/10 , G06T3/40 , G09G5/00 , G09G5/391 , H04N1/393 , H04N5/44 , H04N9/64 , H04N11/20
CPC分类号： G09G5/391 , G06T3/4038 , G09G2340/0407 , G09G2340/0442 , G09G2360/10 , H04N7/01 , H04N7/012 , H04N7/0122 , H04N7/0125 , H04N9/641
摘要： Techniques (Fig. 1) for performing combined scaling, filtering, and/or scan conversion (115,165) are disclosed that reduce the amount of line buffer space required in the overall design of a video processing system. In particular, coefficients (125, 175) from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters (115, 165) are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in a system-on-chip implementations.
摘要翻译：公开了用于执行组合缩放，滤波和/或扫描转换（115,165）的技术（图1），其减少了视频处理系统的整体设计中所需的线路缓冲器空间量。特别地，来自缩放，滤波（平滑/锐化）和扫描转换滤波器（115,165）的全部或子集的系数（125,175）被组合成一个代表系数，其可应用于单个通用算法。因此，实现成本降低，特别是在片上系统实现中。

7. 发明申请

WO2006063337A3 DMA LATENCY COMPENSATION WITH SCALING LINE BUFFER 审中-公开
标题翻译： DMA延迟补偿与缩放线缓冲区
公开(公告)号：WO2006063337A3
公开(公告)日：2008-08-21
申请号：PCT/US2005044885
申请日：2005-12-09
申请人： WIS TECHNOLOGIES INC , SHA LI , HUANG QIFAN
发明人： SHA LI , HUANG QIFAN
IPC分类号： G06F17/00 , G06F13/28 , G06T1/00 , G06T1/60 , G09G5/00 , G09G5/36
CPC分类号： G09G5/395 , G09G5/391
摘要： A video processing system configured with DMA latency compensation is disclosed. This compensation helps minimize or otherwise mitigate shortages of data to the display, thereby improving the quality of displayed video. A relatively small line buffer is used to stage data for video processing. Should an underflow of data occur (where the buffer reading process is ahead of the buffer writing process), data is read from the previous line buffer. This not only prevents shortages of data to the display, but also provides data that is more likely to be relevant to the actual scene being displayed (as compared to random data).
摘要翻译：公开了配置有DMA等待时间补偿的视频处理系统。该补偿有助于最小化或以其他方式减少数据到显示器的短缺，从而提高显示视频的质量。使用相对小的行缓冲器来进行视频处理的数据。如果数据发生下溢（缓冲区读取处理超过缓冲区写入过程），则从前一行缓冲区读取数据。这不仅可以防止显示数据的短缺，而且可以提供更可能与正在显示的实际场景相关的数据（与随机数据相比）。

8. 发明申请

WO2005112434A2 NOISE FILTER FOR VIDEO PROCESSING 审中-公开
标题翻译：用于视频处理的噪声滤波器
公开(公告)号：WO2005112434A2
公开(公告)日：2005-11-24
申请号：PCT/US2005/015402
申请日：2005-05-03
申请人： WIS TECHNOLOGIES, INC. , ZENG, Weimin , SHA, Li , ZHU, Ping
发明人： ZENG, Weimin , SHA, Li , ZHU, Ping
IPC分类号： H04N5/217
CPC分类号： H04N5/21 , H04N19/117 , H04N19/14
摘要： A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.
摘要翻译：用于视频处理系统的噪声滤波器包括块选择器，成本计算器，成本表，成本比较器和系数滤波器。块选择器被耦合以从量化单元接收数据并且选择用于额外滤波的块。所选择的块被提供给成本计算器使用成本表确定块中的每个系数的成本，并且将成本相加。成本比较器将总和比较为阈值，并且如果总数大于预设阈值，则使用系数滤波器对系数进行滤波。然后，VLC单元的噪声滤波器输出滤波器数据。

9. 发明申请

WO2007064341A2 COMBINED SCALING, FILTERING, AND SCAN CONVERSION 审中-公开
标题翻译：组合缩放，过滤和扫描转换
公开(公告)号：WO2007064341A2
公开(公告)日：2007-06-07
申请号：PCT/US2005/044685
申请日：2005-12-09
申请人： WIS TECHNOLOGIES, INC. , HUANG, Qifan , TIAN, Yu, T.
发明人： HUANG, Qifan , TIAN, Yu, T.
IPC分类号： G06F17/10
CPC分类号： G09G5/391 , G06T3/4038 , G09G2340/0407 , G09G2340/0442 , G09G2360/10 , H04N7/01 , H04N7/012 , H04N7/0122 , H04N7/0125 , H04N9/641
摘要： Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce the amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduce, particularly in a system-on-chip implementations.
摘要翻译：公开了用于执行组合缩放，滤波和/或扫描转换的技术，其减少了视频处理系统的整体设计所需的行缓冲器空间量。特别地，将来自缩放，滤波（平滑/锐化）和扫描转换滤波器的全部或子集的系数组合成可以在单个通用算法中应用的一个代表系数。因此，实现成本降低，特别是在片上系统实现方面。

10. 发明申请

WO2005111856A3 SYSTEM AND METHOD FOR RAPIDLY SCALING AND FILTERING VIDEO DATA 审中-公开
标题翻译：用于快速缩放和过滤视频数据的系统和方法
公开(公告)号：WO2005111856A3
公开(公告)日：2006-12-21
申请号：PCT/US2005015275
申请日：2005-05-03
申请人： WIS TECHNOLOGIES INC , SHA LI , HUANG QIFAN
发明人： SHA LI , HUANG QIFAN
IPC分类号： H04N7/01 , G06F17/14 , H04N11/20
CPC分类号： G06T3/4084 , G06T5/20 , G06T2200/28
摘要： This invention relates generally to hardware (100) for scaling and filtering (106, 114) video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware (100) is designed so that scaling and filtering operations (106, 114) are combined and performed simultaneously where possible to speed manipulation of the video data. Efficient design of the system allows memory buffers (112, 110) and logic gates to be shared or eliminated to reduce the size, cost and power requirements of the hardware implementation.
摘要翻译：本发明一般涉及用于缩放和滤波（106,114）视频数据的硬件（100），更具体地涉及用于加速数字视频数据的缩放和滤波操作的算法和技术。硬件（100）被设计成使得缩放和滤波操作（106,114）在可能的情况下同时组合和执行以加速对视频数据的操纵。系统的高效设计允许共享或消除存储器缓冲器（112,110）和逻辑门以减小硬件实现的尺寸，成本和功率要求。

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