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1. 发明申请

WO1994003916A1 METHOD OF MANUFACTURING COLD CATHODES 审中-公开
标题翻译：制造冷阴极的方法
公开(公告)号：WO1994003916A1
公开(公告)日：1994-02-17
申请号：PCT/GB1993001650
申请日：1993-08-04
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard , BOSWELL, Emily
发明人： ISIS INNOVATION LIMITED
IPC分类号： H01J09/02
CPC分类号： H01J9/025 , H01J2209/0226
摘要： A method of making a cold cathode comprises providing a body of a semiconductor e.g. of silicon having a surface including at least one projection, and subjecting the surface to anodic etching, e.g. to produce thereon a porous layer of silicon fibrils.
摘要翻译：制造冷阴极的方法包括提供半导体的主体，例如的硅，其表面包括至少一个突起，并且对所述表面进行阳极蚀刻，例如，以在其上产生硅原纤维的多孔层。

2. 发明申请

WO2012136998A1 HETEROGENEOUS INTEGRATION OF GROUP III-V OR II-VI MATERIALS WITH SILICON OR GERMANIUM 审中-公开
标题翻译： III-V或II-VI族材料与硅或锗的异质整合
公开(公告)号：WO2012136998A1
公开(公告)日：2012-10-11
申请号：PCT/GB2012/050758
申请日：2012-04-04
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug , DE GROOT, Cornelis
发明人： WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug , DE GROOT, Cornelis
IPC分类号： H01L21/26 , H01L21/265
CPC分类号： H01L21/225 , H01L21/02381 , H01L21/22 , H01L21/2605 , H01L21/26506 , H01L21/3225 , H01L21/3226 , H01L21/324 , H01L29/16 , H01L29/2003 , H01L29/225 , H01L29/267 , H01L29/36
摘要： Substrates for an electronic circuit and device manufacturing methods are disclosed. According to an embodiment, the substrate comprises: a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material. The wafer may be formed from Cz silicon or Cz germanium, for example.
摘要翻译：公开了用于电子电路和器件制造方法的衬底。根据实施例，衬底包括：浸渍有形成晶片的材料的带隙内形成一个或多个深能级的杂质的硅或锗晶片，其中所述深能级中的至少一个位于至少0.3 如果电平是受电子电平，则eV远离导带，如果电平是施主电平或离价带至少0.3eV; 以及形成在所述晶片的表面上的器件层，所述器件层包括形成在周期表III-V族或II-VI族材料层中的电子功能元件。晶片可以由例如Cz硅或Cz锗形成。

3. 发明申请

WO2009034362A1 SUBSTRATE FOR HIGH FREQUENCY INTEGRATED CIRCUIT 审中-公开
标题翻译：高频集成电路基板
公开(公告)号：WO2009034362A1
公开(公告)日：2009-03-19
申请号：PCT/GB2008/003131
申请日：2008-09-15
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard , MALLIK, Kanad , FALSTER, Robert, James
发明人： WILSHAW, Peter, Richard , MALLIK, Kanad , FALSTER, Robert, James
IPC分类号： H01L21/22 , H01L21/762 , H01L29/167
CPC分类号： H01L21/221 , H01L21/76251 , H01L29/167
摘要： A substrate for a high frequency integrated circuit is described, comprising: a silicon wafer comprising impurities of a type that form one or more deep energy levels within the band gap of the silicon forming the silicon wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and an electrically insulating silicon oxide layer, formed on a surface of the silicon wafer and providing an outer surface on which a device layer may be formed, said silicon oxide layer having the property of preventing diffusion of said impurities through it. Alternative arrangements may use a different diffusion barrier layer between the silicon wafer and device layer with an additional diffusion barrier layer encapsulating the silicon wafer layer and/or device layer. Associated methods of manufacture are described.
摘要翻译：描述了一种用于高频集成电路的衬底，包括：硅晶片，其包括在形成硅晶片的硅的带隙内形成一个或多个深能级的类型的杂质，其中所述深能级中的至少一个如果电平是施主电平或离电荷带至少0.3eV远离导带至少0.3eV，如果电平是受体电平; 以及电绝缘性氧化硅层，其形成在所述硅晶片的表面上并且提供可在其上形成器件层的外表面，所述氧化硅层具有防止所述杂质通过其扩散的性质。可选择的布置可以在硅晶片和器件层之间使用不同的扩散阻挡层，其中附加的扩散阻挡层封装硅晶片层和/或器件层。描述了相关的制造方法。

4. 发明申请

WO2012137000A1 PROCESSING A WAFER FOR AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：处理电子电路的波形
公开(公告)号：WO2012137000A1
公开(公告)日：2012-10-11
申请号：PCT/GB2012/050760
申请日：2012-04-04
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug
发明人： WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug
IPC分类号： H01L21/26 , H01L21/265 , H01L21/322
CPC分类号： H01L21/225 , H01L21/02381 , H01L21/22 , H01L21/2605 , H01L21/26506 , H01L21/3225 , H01L21/3226 , H01L21/324 , H01L29/16 , H01L29/2003 , H01L29/225 , H01L29/267 , H01L29/36
摘要： According to a disclosed embodiment, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and pre-processing the silicon wafer, prior to or after said impregnation step, so that precipitation of oxide during, after, or during and after, said impregnating step is suppressed.
摘要翻译：根据所公开的实施例，提供了一种处理用于电子电路的基板的硅晶片的方法，包括：在硅的带隙内形成一个或多个深能级的杂质浸渍硅晶片，其中如果该电平是受电子电平，则该电平是施主电平或离价带至少0.3eV的至少一个所述深能级位于远离导带的至少0.3eV处; 并且在所述浸渍步骤之前或之后对硅晶片进行预处理，从而抑制在所述浸渍步骤期间，之后或期间和之后的氧化物的沉淀。

5. 发明申请

WO2012136999A1 CONTROLLING IMPURITIES IN A WAFER FOR AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：控制电子电路的浪费
公开(公告)号：WO2012136999A1
公开(公告)日：2012-10-11
申请号：PCT/GB2012/050759
申请日：2012-04-04
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug , ASHBURN, Peter , DE GROOT, Cornelis
发明人： WILSHAW, Peter , MALLIK, Kanad , JORDAN, Doug , ASHBURN, Peter , DE GROOT, Cornelis
IPC分类号： H01L21/26 , H01L21/265
CPC分类号： H01L21/225 , H01L21/02381 , H01L21/22 , H01L21/2605 , H01L21/26506 , H01L21/3225 , H01L21/3226 , H01L21/324 , H01L29/16 , H01L29/2003 , H01L29/225 , H01L29/267 , H01L29/36
摘要： Methods of processing a silicon wafer for an electronic circuit, substrates for an electronic circuit, and device manufacturing methods are disclosed. According to an embodiment the method of processing a silicon wafer comprises impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.
摘要翻译：公开了用于电子电路的硅晶片的处理方法，电子电路用基板及其制造方法。根据实施例，处理硅晶片的方法包括用在硅的带隙内形成一个或多个深能级的杂质浸渍硅晶片，其中所述深能级中的至少一个位于距离如果该水平是受体水平，则该水平是施主水平或离价带至少0.3eV的导带，其中：所述浸渍步骤以这样的方式进行，使得所述杂质的最大浓度所述硅晶片和所述硅晶片中所述杂质的平均浓度小于7:1。

6. 发明申请

WO0203894A8 AN IMPROVED BONE-IMPLANT PROSTHESIS 审中-公开
标题翻译：改进的骨髓移植
公开(公告)号：WO0203894A8
公开(公告)日：2002-06-06
申请号：PCT/GB0103189
申请日：2001-07-12
申请人： ISIS INNOVATION , WILSHAW PETER RICHARD , PALSGARD ANNA EVA MARIA
发明人： WILSHAW PETER RICHARD , PALSGARD ANNA EVA MARIA
IPC分类号： A61F2/00 , A61F2/30 , A61F2/32 , A61F2/36 , A61F2/40 , A61K6/027 , A61L27/30 , A61L27/32 , A61L27/54 , C23C28/00
CPC分类号： C23C28/322 , A61F2/30756 , A61F2/30767 , A61F2/3094 , A61F2/32 , A61F2/3603 , A61F2002/30649 , A61F2002/30894 , A61F2002/30929 , A61F2002/4007 , A61F2310/00017 , A61F2310/00023 , A61F2310/00029 , A61F2310/00047 , A61F2310/00179 , A61F2310/00431 , A61F2310/00604 , A61F2310/00796 , A61F2310/00928 , A61F2310/00976 , A61F2310/00982 , A61L27/306 , A61L27/32 , A61L27/54 , A61L2300/112 , C23C28/321 , C23C28/345 , C23C28/347
摘要： A prosthesis is disclosed at least of the surface of which is of metal, said metal being covered by a layer of aluminium oxide which comprises phosphate and/or pores containing bioactive material, optionally with a layer of aluminium or an alloy thereof between the metal and the porous aluminium oxide layer.
摘要翻译：公开了至少其表面为金属的假体，所述金属被一层氧化铝覆盖，所述氧化铝层包括磷酸盐和/或包含生物活性材料的孔，任选地在所述金属和多孔氧化铝层。

7. 发明申请

WO0215214A2 FIELD EMITTER DEVICES INCORPORATING AN IMPROVED BALLAST RESISTOR 审中-公开
标题翻译：并入改进的压电电阻器的场致发器件
公开(公告)号：WO0215214A2
公开(公告)日：2002-02-21
申请号：PCT/GB0103591
申请日：2001-08-10
申请人： ISIS INNOVATION , WILSHAW PETER RICHARD , HOLLAND EDWARD ROBERT , LI YAGANG
发明人： WILSHAW PETER RICHARD , HOLLAND EDWARD ROBERT , LI YAGANG
IPC分类号： H01C17/16 , H01J1/304 , H01J9/02
CPC分类号： H01C17/16 , H01J1/3044 , H01J2201/319
摘要： A field emitter device is disclosed which comprises a layer of a non-conducting support material having thereon successive layers of an address electrode, a dielectric anodic metal oxide layer and, optionally, lastly, a grid electrode, the dielectric anodic metal oxide layer possessing an array of pores extending from the surface in contact with the grid electrode to the address electrode, said pores containing wires which extend from the address electrode to the surface of the anodic metal oxide layer in contact with the grid electrode, at least one section along the wires not in contact with the address electrode being formed of a resistive material.
摘要翻译：公开了一种场致发射器件，其包括一层非导电支撑材料，其上具有寻址电极，电介质阳极金属氧化物层和任选地最后一个栅格电极的连续层，该电介质阳极金属氧化物层具有从与栅格电极接触的表面延伸到寻址电极的孔的阵列，所述孔包含从寻址电极延伸到阳极金属氧化物层与栅电极接触的表面的电线，沿着与地址电极不接触的电线由电阻材料形成。

8. 发明申请

WO2009125187A1 A METHOD OF ETCHING SILICON WAFERS 审中-公开
标题翻译：蚀刻硅氧烷的方法
公开(公告)号：WO2009125187A1
公开(公告)日：2009-10-15
申请号：PCT/GB2009/000930
申请日：2009-04-09
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard
发明人： WILSHAW, Peter, Richard
IPC分类号： H01L31/0368 , H01L31/18
CPC分类号： H01L31/186 , H01L31/03685 , H01L31/1868 , Y02E10/50 , Y02P70/521
摘要： A method for the reduction of dislocations in silicon is described, the method comprising the steps of etching said silicon so as to selectively remove at least a part of the dislocation core extending into said silicon material from a free surface thereof. A further step of treating said etched silicon material by a technique to electrically passivate a surface formed due to removal of said at least part of the dislocation may also be carried out.
摘要翻译：描述了用于减少硅中位错的方法，该方法包括以下步骤：蚀刻所述硅，以从其自由表面选择性地去除延伸到所述硅材料中的至少一部分位错核。还可以进行通过由于去除所述至少部分位错而形成的表面电钝化的技术来处理所述蚀刻的硅材料的另一步骤。

9. 发明申请

WO2002015214A3 FIELD EMITTER DEVICES INCORPORATING AN IMPROVED BALLAST RESISTOR 审中-公开
公开(公告)号：WO2002015214A3
公开(公告)日：2002-02-21
申请号：PCT/GB2001/003591
申请日：2001-08-10
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard , HOLLAND, Edward, Robert , LI, Yagang
发明人： WILSHAW, Peter, Richard , HOLLAND, Edward, Robert , LI, Yagang
IPC分类号： H01J1/304
摘要： A field emitter device is disclosed which comprises a layer of a non-conducting support material having thereon successive layers of an address electrode, a dielectric anodic metal oxide layer and, optionally, lastly, a grid electrode, the dielectric anodic metal oxide layer possessing an array of pores extending from the surface in contact with the grid electrode to the address electrode, said pores containing wires which extend from the address electrode to the surface of the anodic metal oxide layer in contact with the grid electrode, at least one section along the wires not in contact with the address electrode being formed of a resistive material.

10. 发明申请

WO1996006443A1 FIELD EMITTER STRUCTURES 审中-公开
标题翻译：现场发射机结构
公开(公告)号：WO1996006443A1
公开(公告)日：1996-02-29
申请号：PCT/GB1995001943
申请日：1995-08-16
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard
发明人： ISIS INNOVATION LIMITED
IPC分类号： H01J03/02
CPC分类号： H01J1/3042 , H01J9/025 , H01J2201/319
摘要： A field emitter device comprises a dielectric anodic aluminium oxide layer having pores filled with wires the front ends of which constitute individual field emitting cathodes, a gate electrode overlying a front surface of the layer, and an address electrode overlying a back surface of the layer and in electrical contact with the wires. The problem of short circuit between the gate electrode and the field emitter is overcome by cleaning the pore walls adjacent the gate electrode and/or by selectively dissolving the back ends of individual wires.
摘要翻译：场致发射器件包括介电阳极氧化铝层，其具有填充有导线的孔，其前端构成单个场发射阴极，覆盖该层的前表面的栅电极和覆盖该层后表面的寻址电极，与电线电接触。通过清洁邻近栅电极的孔壁和/或通过选择性地溶解单根线的后端来克服栅电极和场发射极之间的短路问题。

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