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    • 4. 发明申请
    • MINIMIZING POWER CONSUMPTION IN HIGH FREQUENCY DIGITAL CIRCUITS
    • 在高频数字电路中最大限度地降低功耗
    • WO2006018818A1
    • 2006-02-23
    • PCT/IB2005/052715
    • 2005-08-17
    • KONINKLIJKE PHILIPS ELECTRONICS, N.V.U.S. PHILIPS CORPORATIONVISSER, HenkVAUCHER, Cicero
    • VISSER, HenkVAUCHER, Cicero
    • H03K3/0233
    • H03L7/06H03K3/012H03K3/2885H03K3/289
    • A circuit comprises a frequency divider connected to receive respective Igate and hatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends, in part, on these DC-biasing currents. Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption. During calibration, the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency. The DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the self­resonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.
    • 电路包括分频器,其连接以接收相应的Igate和阴影直流偏置电流。 这种分频器在某些频率下将自谐振,该频率部分取决于这些直流偏置电流。 相应的电流源为这些直流偏置电流中的每一个提供可编程的幅度,因此可以影响自谐振频率和总功耗。 在校准期间,分频器被允许自振荡,并且操纵DC偏置电流以使自谐振频率接近某些目标频率。 当分频器的自谐振频率调谐到目标工作频率时,直流偏置电流可以机会地降低,并保持可靠的运行。 在设备的使用寿命期间根据需要重复这种校准。