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1. 发明申请

WO2006129292A3 NPN BIPOLAR TRANSISTOR WITH IMPROVED BASE ACCESS RESISTANCE 审中-公开
标题翻译： NPN双极晶体管，具有改进的基极电阻
公开(公告)号：WO2006129292A3
公开(公告)日：2007-02-22
申请号：PCT/IB2006051767
申请日：2006-06-01
申请人： KONINKL PHILIPS ELECTRONICS NV , TAN POH CHENG , DEIXLER PETER , VAUCHER CICERO SILVEIRA
发明人： TAN POH CHENG , DEIXLER PETER , VAUCHER CICERO SILVEIRA
IPC分类号： H01L29/737 , H01L29/08
CPC分类号： H01L29/7322 , H01L21/8249 , H01L29/0813 , H01L29/7378
摘要： A configuration composed of multiple short emitters still share common DTI regions and a single big piece of base poly. This allows for base current to flow in 4 directions (e.g., 2 dimensions) as opposed to only two. This significantly reduces the base resistance of the transistor that is crucial for better NPN transistor RF performance and high frequency noise performance.
摘要翻译：由多个短发射器组成的配置仍然共享公共DTI区域和单个大块基础聚合物。这允许基极电流在四个方向（例如，二维）上流动，而不是仅两个。这显着降低了对更好的NPN晶体管RF性能和高频噪声性能至关重要的晶体管的基极电阻。

2. 发明申请

WO2006075307A2 MODULAR SWITCHING ARRANGEMENT 审中-公开
标题翻译：模块化开关装置
公开(公告)号：WO2006075307A2
公开(公告)日：2006-07-20
申请号：PCT/IB2006050122
申请日：2006-01-13
申请人： KONINKL PHILIPS ELECTRONICS NV , DARRIET STEPHANE , VAUCHER CICERO S
发明人： DARRIET STEPHANE , VAUCHER CICERO S
CPC分类号： H03K17/74 , H03K17/76
摘要： The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D1/D2, D3/D4) are connected to each other in a mirrored configuration to obtain a basic switching cell. This basic switching cell can be used to build a SPDT switch which in turn can be used to build a DPDT switch or switches of higher complexity. Thereby, high isolation and low power consumption can be achieved with the additional advantage of modularity.
摘要翻译：本发明涉及一种制造这种结构的开关装置和方法，其中第一和第二串联分流二极管结构（D1 / D2，D3 / D4）以镜像配置相互连接以获得基本的开关单元。该基本开关单元可用于构建SPDT开关，该开关又可用于构建更复杂的DPDT开关或开关。因此，可以通过模块化的额外优点实现高隔离度和低功耗。

3. 发明申请

WO2003065586A3 PHASE-LOCKED-LOOP WITH REDUCED CLOCK JITTER 审中-公开
公开(公告)号：WO2003065586A3
公开(公告)日：2003-08-07
申请号：PCT/IB2003/000130
申请日：2003-01-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
发明人： NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
IPC分类号： H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

4. 发明申请

WO03065586A2 PHASE-LOCKED-LOOP WITH REDUCED CLOCK JITTER 审中-公开
标题翻译：带有减速时钟抖动器的锁相环
公开(公告)号：WO03065586A2
公开(公告)日：2003-08-07
申请号：PCT/IB0300130
申请日：2003-01-20
申请人： KONINKL PHILIPS ELECTRONICS NV , NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
发明人： NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
IPC分类号： H03L7/18 , H03L7/089 , H03L7/095 , H03L7/107 , H03L7/197
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/107 , H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
摘要翻译：锁相环（PLL）电路及其控制方法技术领域本发明涉及锁相环（PLL）电路和控制这种PLL电路的方法，其中输入参考信号的频率和从输出振荡信号导出的反馈信号的频率除以从而降低PLL电路的相位检测装置（1）的频率。响应于PLL电路的锁相状态的检测，禁止分频步骤。因此，在实现了相位锁定之后，从循环中除去添加了减小比较频率的额外的参考分频器（6），从而能够增加环路带宽并减小环路内的分频比。

5. 发明申请

WO2006018818A1 MINIMIZING POWER CONSUMPTION IN HIGH FREQUENCY DIGITAL CIRCUITS 审中-公开
标题翻译：在高频数字电路中最大限度地降低功耗
公开(公告)号：WO2006018818A1
公开(公告)日：2006-02-23
申请号：PCT/IB2005/052715
申请日：2005-08-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , VISSER, Henk , VAUCHER, Cicero
发明人： VISSER, Henk , VAUCHER, Cicero
IPC分类号： H03K3/0233
CPC分类号： H03L7/06 , H03K3/012 , H03K3/2885 , H03K3/289
摘要： A circuit comprises a frequency divider connected to receive respective Igate and hatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends, in part, on these DC-biasing currents. Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption. During calibration, the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency. The DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the selfresonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.
摘要翻译：电路包括分频器，其连接以接收相应的Igate和阴影直流偏置电流。这种分频器在某些频率下将自谐振，该频率部分取决于这些直流偏置电流。相应的电流源为这些直流偏置电流中的每一个提供可编程的幅度，因此可以影响自谐振频率和总功耗。在校准期间，分频器被允许自振荡，并且操纵DC偏置电流以使自谐振频率接近某些目标频率。当分频器的自谐振频率调谐到目标工作频率时，直流偏置电流可以机会地降低，并保持可靠的运行。在设备的使用寿命期间根据需要重复这种校准。

6. 发明申请

WO2005093954A1 DEVICE COMPRISING A FREQUENCY DIVIDER 审中-公开
标题翻译：包含频率分路器的装置
公开(公告)号：WO2005093954A1
公开(公告)日：2005-10-06
申请号：PCT/IB2005/050925
申请日：2005-03-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAUCHER, Cicero, S. , APOSTOLIDOU, Melania
发明人： VAUCHER, Cicero, S. , APOSTOLIDOU, Melania
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： Frequency dividers (2) comprising a first transistor circuit (21) with four transistor pairs (31-34, 81-84), two gate pairs (31, 33, 81, 83) and two latch pairs (32, 34, 82, 84) and comprising a second transistor circuit (22) with two transistor pairs (35-36, 85-86) and comprising an impedance circuit (23) have a relatively low frequency reach. By replacing the prior art load resistors in the impedance circuit (23) by active load impedances comprising transistors (37-40, 87-90), the frequency reach of the frequency divider (2) is improved significantly. An impedance (41-44) coupled to the emitter of a transistor (37-40, 87-90) defines the operation frequency range of the frequency divider (2), and an impedance (45-48) coupled to the basis of a transistor (37-40, 87-90) allows the frequency divider (2) to be tuned for maximum operation frequency.
摘要翻译：分频器（2）包括具有四个晶体管对（31-34,81-84），两个栅极对（31,33,81,83）和两个锁存对（32,34,82,82）的第一晶体管电路（21） 84）并且包括具有两个晶体管对（35-36,85-86）的第二晶体管电路（22），并且包括阻抗电路（23）具有相对较低的频率范围。通过用包括晶体管（37-40,87-90）的有源负载阻抗代替阻抗电路（23）中的现有技术的负载电阻器，分频器（2）的频率范围得到显着改善。耦合到晶体管（37-40,87-90）的发射极的阻抗（41-44）限定了分频器（2）的工作频率范围，耦合到晶体管（37-40,87-90）允许调谐器（2）调整最大工作频率。

7. 发明申请

WO2004030365A1 HEAD END HAVING A LOW NOISE CONVERTER WITH CHANNEL PRESELECTING FREQUENCY MULTIPLEXOR 审中-公开
标题翻译：具有通道选择频率多路复用器的低噪声转换器
公开(公告)号：WO2004030365A1
公开(公告)日：2004-04-08
申请号：PCT/IB2003/050001
申请日：2003-08-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HOOIJMANS, Pieter, W. , VAUCHER, Cicero, S.
发明人： HOOIJMANS, Pieter, W. , VAUCHER, Cicero, S.
IPC分类号： H04N7/20
CPC分类号： H04H40/90 , H04N7/106 , H04N7/20
摘要： A head end (7) comprises a low noise converter (2) for providing signal bands including channels to one or more user units (3). The low noise converter is arranged as a low noise channel converter (2), which includes frequency multiplexing means (6) for multiplexing one or more user pre-selected channels to the user units (3). By effecting pre-selection in the low noise channel converter (2) the connection between the head end (7) and the user units (3) only contains a single communication medium (5), generally an already installed coaxial cable (5). Wanted channels for example for watching one television program and simultaneously recording another program are pre-selected and at the side of the low noise block put on the one cable.
摘要翻译：头端（7）包括用于向一个或多个用户单元（3）提供包括信道的信号频带的低噪声转换器（2）。低噪声转换器被布置为低噪声信道转换器（2），其包括用于将一个或多个用户预先选择的信道复用到用户单元（3）的频率复用装置（6）。通过在低噪声信道转换器（2）中进行预选择，头端（7）和用户单元（3）之间的连接仅包含通常已经安装的同轴电缆（5）的单个通信介质（5）。例如用于观看一个电视节目并同时录制另一节目的通道被预先选择，并且在放置在一个电缆上的低噪声块的一侧。

8. 发明申请

WO2004010444A1 MULTI-TAP COIL 审中-公开
标题翻译：多针线圈
公开(公告)号：WO2004010444A1
公开(公告)日：2004-01-29
申请号：PCT/IB2003/002852
申请日：2003-06-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DOLMANS, Wilhelmus, M., C. , VAUCHER, Cicero, S.
发明人： DOLMANS, Wilhelmus, M., C. , VAUCHER, Cicero, S.
IPC分类号： H01F17/00
CPC分类号： H03B5/1847 , H01F17/0006 , H01F21/12 , H01F2021/125 , H01L27/08 , H03B5/1215 , H03B5/1231 , H03B5/124
摘要： The invention relates to multi-band resonator circuits with inductors and capacitors. These resonator circuits are realized on integrated circuits. The inductors are realized according to the invention within one single coil comprising a center (2) tap and intermediate taps (4, 6).
摘要翻译：本发明涉及具有电感器和电容器的多频带谐振器电路。这些谐振电路在集成电路上实现。电感器根据本发明在包括中心（2）抽头和中间抽头（4,6）的单个线圈内实现。

9. 发明申请

WO2006075307A3 MODULAR SWITCHING ARRANGEMENT 审中-公开
公开(公告)号：WO2006075307A3
公开(公告)日：2006-07-20
申请号：PCT/IB2006/050122
申请日：2006-01-13
申请人： NXP B.V. , DARRIET, Stephane , VAUCHER, Cicero, S.
发明人： DARRIET, Stephane , VAUCHER, Cicero, S.
IPC分类号： H03K17/74 , H03K17/76
摘要： The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D1/D2, D3/D4) are connected to each other in a mirrored configuration to obtain a basic switching cell. This basic switching cell can be used to build a SPDT switch which in turn can be used to build a DPDT switch or switches of higher complexity. Thereby, high isolation and low power consumption can be achieved with the additional advantage of modularity.

10. 发明申请

WO2004093355A1 RECEIVER HAVING A CALIBRATING SYSTEM 审中-公开
标题翻译：具有校准系统的接收器
公开(公告)号：WO2004093355A1
公开(公告)日：2004-10-28
申请号：PCT/IB2004/050413
申请日：2004-04-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAUCHER, Cicero, S. , STIKVOORT, Eduard, F.
发明人： VAUCHER, Cicero, S. , STIKVOORT, Eduard, F.
IPC分类号： H04B17/00
CPC分类号： H04B1/28 , H03J1/0008 , H03J2200/29 , H03L7/16
摘要： A calibrating system for a receiver receiving an input signal (Rf) having an input frequency (fRf) and working in a receiving mode (R) and in a calibrating mode (C) comprising an intermediate frequency circuit (IF) coupled to a first mixer and comprising a bulk acoustic wave filter (BAW) determining the intermediate frequency (BAWf). The calibrating system further comprises a level detecting circuit (LD) coupled to the intermediate frequency circuit (IF) via a first switch (S1) in the calibrating mode (C) for determining an amplitude of the intermediate frequency signal. The receiver includes a tuning control processor (TC) coupled to the first synthesizer (LO1) and to the second synthesizer (L02) controlling the frequencies generated by said synthesizers (LO1, L02). A level detecting circuit (LD) is coupled to the intermediate frequency circuit (IF) for determining an amplitude of the intermediate frequency signal and providing a signal indicative for said amplitude to the tuning control processor (TC). The system further comprises a register (Reg) coupled to the tuning control processor (TC) for memorizing a number corresponding to the intermediate frequency (BAWf), the number being used as a correction factor for the first and second synthesizers (LO I, L02) in the receiving mode (R).
摘要翻译：一种用于接收接收具有输入频率（fRf）并且以接收模式（R）工作的校准模式（C））的输入信号（Rf）的接收机的校准系统，包括耦合到第一混频器的中频电路（IF）并且包括确定中间频率（BAWf）的体声波滤波器（BAW）。校准系统还包括经由校准模式（C）中的第一开关（S1）耦合到中频电路（IF）的电平检测电路（LD），用于确定中频信号的幅度。接收机包括耦合到第一合成器（LO1）的调谐控制处理器（TC）和控制由所述合成器（LO1，L02）产生的频率的第二合成器（L02）。电平检测电路（LD）耦合到中频电路（IF），用于确定中频信号的幅度，并向调谐控制处理器（TC）提供指示所述振幅的信号。该系统还包括耦合到调谐控制处理器（TC）的寄存器（Reg），用于存储对应于中间频率（BAWf）的数字，该数字被用作第一和第二合成器（LO I，L02 ）在接收模式（R）中。

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