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1. 发明申请

WO2004097837A2 METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN 审中-公开
标题翻译：用于改进终止读取标记的双细胞存储器设备操作的方法
公开(公告)号：WO2004097837A2
公开(公告)日：2004-11-11
申请号：PCT/US2004/007124
申请日：2004-03-08
申请人： ADVANCED MICRO DEVICES, INC. , HAMILTON, Darlene, G. , TANPAIROJ, Kulachet , HSIA, Edward , MADHANI, Alykhan , LEE, Mimi
发明人： HAMILTON, Darlene, G. , TANPAIROJ, Kulachet , HSIA, Edward , MADHANI, Alykhan , LEE, Mimi
IPC分类号： G11C
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A method of programming a dual cell memory device (6) having a first charge storing cell (38, 40) and a second charge storing cell (38, 40). According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.
摘要翻译：一种编程具有第一电荷存储单元（38,40）和第二电荷存储单元（38,40）的双单元存储器件（6）的方法。根据该方法的一个方面，该方法可以包括过度擦除第一和第二电荷存储单元，以使存储器件的擦除状态阈值电压低于自然状态阈值电压。根据该方法的另一方面，该方法可以包括将第一和第二电荷存储单元编程为相同的数据状态，并验证第二编程电荷存储单元存储对应于数据状态的电荷。如果验证失败，则电荷存储单元可以被重新脉冲。

2. 发明申请

WO2005038815A1 MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL 审中-公开
标题翻译：存储器件和使用正栅极应力来恢复过度电池的方法
公开(公告)号：WO2005038815A1
公开(公告)日：2005-04-28
申请号：PCT/US2004/030694
申请日：2004-09-16
申请人： ADVANCED MICRO DEVICES, INC. , HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
发明人： HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells (10) includes pre-programming (100) the plurality of memory cells (10), applying an erase pulse (110) to the plurality of memory cells (10) followed by an erase verification (120). The erase verification (120) is followed by soft programming (135) any memory cells having a threshold voltage below a predetermined minimum level (V TMIN ) and applying a positive gate stress (130) to the plurality of memory cells (10). The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储单元（10）组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括：对所述多个存储器单元（10）进行预编程（100），向所述多个存储器单元（10）施加擦除脉冲（110）多个存储器单元（10），随后进行擦除验证（120）。擦除验证（120）之后是具有低于预定最小电平（VTMIN）的阈值电压并向多个存储单元（10）施加正门应力（130）的任何存储器单元（135）进行软编程（135）。擦除方法可以防止过压，并提供紧固的阈值电压分布。

3. 发明申请

WO2019046386A1 SLC CACHE MANAGEMENT 审中-公开
公开(公告)号：WO2019046386A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/048477
申请日：2018-08-29
申请人： MICRON TECHNOLOGY, INC. , TANPAIROJ, Kulachet , HUANG, Jianmin
发明人： TANPAIROJ, Kulachet , HUANG, Jianmin , JEAN, Sebastien Andre , MUCHHERLA, Kishore Kumar , MALSHE, Ashutosh
IPC分类号： G06F12/0868 , G06F13/42
摘要： Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

4. 发明申请

WO2019046326A1 READ VOLTAGE CALIBRATION BASED ON HOST IO OPERATIONS 审中-公开
公开(公告)号：WO2019046326A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/048383
申请日：2018-08-28
申请人： MICRON TECHNOLOGY, INC. , RATNAM, Sampath , TANPAIROJ, Kulachet
发明人： RATNAM, Sampath , TANPAIROJ, Kulachet , MALSHE, Ashutosh , MUCHHERLA, Kishore Kumar , SINGIDI, Harish Reddy , FEELEY, Peter Sean , LUO, Ting
IPC分类号： G11C16/26 , G11C16/30
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

5. 发明申请

WO2008082824A2 MULTI-LEVEL OPERATION IN DUAL ELEMENT CELLS USING A SUPPLEMENTAL PROGRAMMING LEVEL 审中-公开
标题翻译：使用补充编程级别的双元素细胞中的多级操作
公开(公告)号：WO2008082824A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/085837
申请日：2007-11-29
申请人： SPANSION LLC , HAMILTON, Darlene , BATHUL, Fatima , TANPAIROJ, Kulachet , LI, Du
发明人： HAMILTON, Darlene , BATHUL, Fatima , TANPAIROJ, Kulachet , LI, Du
IPC分类号： G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3418 , G11C16/3427
摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells (100) in a memory device. In multi-bit memory cells (100), programming one element (120) can affect the second element (122). Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element (120) while a second element (122) of the same memory cell (100) is unprogrammed. Memory cell elements (120, 122) can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.
摘要翻译：所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元（100）的系统和/或方法。在多位存储器单元（100）中，编程一个元件（120）可以影响第二元件（122）。元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。当相同存储单元（100）的第二元件（122）未被编程时，高电荷电平被编程到第一元件（120）中，这种效果可能是显着的。可以使用额外的电荷电平对存储单元元件（120,122）进行编程，以减轻这种影响。例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合，和状态依赖程序干扰。

6. 发明申请

WO2004097837A3 METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN 审中-公开
标题翻译：用于改进终止读取标记的双细胞存储器设备操作的方法
公开(公告)号：WO2004097837A3
公开(公告)日：2005-02-10
申请号：PCT/US2004007124
申请日：2004-03-08
申请人： ADVANCED MICRO DEVICES INC , HAMILTON DARLENE G , TANPAIROJ KULACHET , HSIA EDWARD , MADHANI ALYKHAN , LEE MIMI
发明人： HAMILTON DARLENE G , TANPAIROJ KULACHET , HSIA EDWARD , MADHANI ALYKHAN , LEE MIMI
IPC分类号： G11C20060101 , G11C11/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A method of programming a dual cell memory device (6) having a first charge storing cell (38, 40) and a second charge storing cell (38, 40). According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.
摘要翻译：一种编程具有第一电荷存储单元（38,40）和第二电荷存储单元（38,40）的双单元存储器件（6）的方法。根据该方法的一个方面，该方法可以包括过度擦除第一和第二电荷存储单元，以使存储器件的擦除状态阈值电压低于自然状态阈值电压。根据该方法的另一方面，该方法可以包括将第一和第二电荷存储单元编程为相同的数据状态，并验证第二编程电荷存储单元存储对应于数据状态的电荷。如果验证失败，则电荷存储单元可以被重新脉冲。

7. 发明申请

WO2019046548A1 FLASH MEMORY BLOCK RETIREMENT POLICY 审中-公开
公开(公告)号：WO2019046548A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/048788
申请日：2018-08-30
申请人： SINGIDI, Harish Reddy , CARIELLO, Giuseppe , HE, Deping , STOLLER, Scott Anthony , BATUTIS, Devin , THOMSON, Preston , HUANG, Jianmin , TANPAIROJ, Kulachet , ZHANG, John , LUO, Xiangang , LUO, Ting
发明人： SINGIDI, Harish Reddy , CARIELLO, Giuseppe , HE, Deping , STOLLER, Scott Anthony , BATUTIS, Devin , THOMSON, Preston
IPC分类号： G11C16/34 , G11C16/26 , G11C29/42 , G11C29/52
摘要： Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

8. 发明申请

WO2008082824A3 MULTI-LEVEL OPERATION IN DUAL ELEMENT CELLS USING A SUPPLEMENTAL PROGRAMMING LEVEL 审中-公开
标题翻译：使用一个补充编程水平在双元件单元中的多级操作
公开(公告)号：WO2008082824A3
公开(公告)日：2008-11-13
申请号：PCT/US2007085837
申请日：2007-11-29
申请人： SPANSION LLC , HAMILTON DARLENE , BATHUL FATIMA , TANPAIROJ KULACHET , LI DU
发明人： HAMILTON DARLENE , BATHUL FATIMA , TANPAIROJ KULACHET , LI DU
IPC分类号： G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3418 , G11C16/3427
摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells (100) in a memory device. In multi-bit memory cells (100), programming one element (120) can affect the second element (122). Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element (120) while a second element (122) of the same memory cell (100) is unprogrammed. Memory cell elements (120, 122) can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.
摘要翻译：所要求保护的主题提供了便于编程和读取存储器设备中的多级多位存储单元（100）的系统和/或方法。在多位存储单元（100）中，编程一个元件（120）会影响第二元件（122）。元件的某些组合可能导致过度的互补位干扰，依赖于状态的非均匀电荷损失和依赖于状态的编程干扰，从而降低存储器件的可靠性。这样的效应可以在将高电荷电平编程到第一元件（120）中而对同一存储器单元（100）的第二元件（122）未编程时明显。存储单元元件（120,122）可以使用额外的电荷电平来编程以减轻这种影响。例如，可能使用四个电荷电平的十六个不同元件组合可以使用五个电荷电平映射到二十五个可能元件组合的子集，从而避免元件组合可能产生过多的互补位干扰，取决于状态的非均匀电荷损失，和状态相关的编程干扰。

9. 发明申请

WO2004095469A1 METHOD OF PROGRAMMING DUAL CELL MEMORY DEVICE TO STORE MULTIPLE DATA STATES PER CELL 审中-公开
标题翻译：编程双细胞存储器件的方法来存储每个细胞的多个数据状态
公开(公告)号：WO2004095469A1
公开(公告)日：2004-11-04
申请号：PCT/US2004/007026
申请日：2004-03-08
申请人： ADVANCED MICRO DIVICES, INC. , HAMILTON, Darlene, G. , TANPAIROJ, Kulachet , HSIA, Edward , HE, Yi
发明人： HAMILTON, Darlene, G. , TANPAIROJ, Kulachet , HSIA, Edward , HE, Yi
IPC分类号： G11C11/56
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10
摘要： A method of programming a multi-level, dual cell memory device (6). The method includes independently programming a first charge storing cell (38, 40) and a second charge storing cell (38, 40) to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.

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