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1. 发明申请

WO2003043057A2 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
标题翻译：基于适当使用电感效应的合成策略
公开(公告)号：WO2003043057A2
公开(公告)日：2003-05-22
申请号：PCT/US2002/036342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ESCOVAR, Rafael
发明人： SUAYA, Roberto , ESCOVAR, Rafael
IPC分类号： H01L
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.
摘要翻译：提供了一种优化布线布局的传播速度的方法。通常，该方法考虑并使用由并联接地线包围的信号线上的高速信号的传播引起的电感效应。特别地，可以调整限定布线布局的物理参数之一，以在布线布局中产生使信号传播速度最大化的rlc关系。调整的物理参数可以是例如信号线和接地线之间的线间隔。公开的方法也可以应用于具有多个分支（例如时钟树）的布线布局。在此上下文中，可以使用所公开的方法来优化第一分支。然后可以调节下行分支，使得分支之间的结处的阻抗基本相等。

2. 发明申请

WO03043057B1 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
标题翻译：基于适当使用电感效应的综合策略
公开(公告)号：WO03043057B1
公开(公告)日：2003-10-30
申请号：PCT/US0236342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORP , SUAYA ROBERTO , ESCOVAR RAFAEL
发明人： SUAYA ROBERTO , ESCOVAR RAFAEL
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A method of optimizing the propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed . The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires. The disclose method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedance at the junctions between the branches are substantially equal.
摘要翻译：提供了一种优化布线布局上的传播速度的方法。通常，该方法考虑并使用由平行接地线包围的信号线上的高速信号传播引起的电感效应。具体而言，可以调整限定布线布局的物理参数之一，以在布线布局中创建最大化信号传播速度的rlc关系。被调整的物理参数可以是例如信号线和地线之间的线分离。所公开的方法也可以应用于具有多个分支的布线布局，例如时钟树。在这种情况下，可以使用所公开的方法优化第一分支。然后可以调整下游分支，使得分支之间的连接处的阻抗基本相等。

3. 发明申请

WO2009114483A1 HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE 审中-公开
标题翻译：多层导电基板存在的高频VLSI互连和有效电感阻抗提取
公开(公告)号：WO2009114483A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/036571
申请日：2009-03-09
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto
发明人： SUAYA, Roberto
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068
摘要： Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
摘要翻译：本文公开了用于提取电路设计的阻抗的方法，装置和系统的实施例。所公开的实施例中的一些在计算上是有效的并且可以在存在多层导电衬底的情况下准确地计算VLSI互连和/或有意感应器的频率相关阻抗。在某些实施例中，所得到的精度和CPU时间减少是绿色功能方法的结果，其具有正确的准静态极限，对绿色函数的修正离散复数图像逼近，以及连续偶极子扩展以评估磁矢量势与VLSI互连和有意的电感相关的距离。

4. 发明申请

WO2008137774A2 MODELING THE SKIN EFFECT USING EFFICIENT CONDUCTION MODE TECHNIQUES 审中-公开
标题翻译：使用有效的导电模式技术建模皮肤的影响
公开(公告)号：WO2008137774A2
公开(公告)日：2008-11-13
申请号：PCT/US2008/062547
申请日：2008-05-02
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ORTIZ, Salvador
发明人： SUAYA, Roberto , ORTIZ, Salvador
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78
摘要： Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrand's for calculating the matrix elements into simplified terms that are less computationally intensive than the integrand's and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media).
摘要翻译：这里描述了用于提取用于电路设计的各种高频参数的方法的实施例。在一个示例性实施例中，接收指示电路设计中的导体的至少几何布局的电路设计信息和用于电路设计的期望的操作频率。定义表示在期望的操作频率下的导体中的电流的分布函数的导通模式。产生包括基于限定的导电模式的矩阵元素的导电模式矩阵。一个或多个矩阵元素的值通过将被积函数分解为将矩阵元素计算为比被积函数计算密集程度更低的简化术语并计算简化术语的值来计算。一个或多个矩阵元素的值可以被存储（例如，在一个或多个计算机可读介质上）。

5. 发明申请

WO2008137774A3 MODELING THE SKIN EFFECT USING EFFICIENT CONDUCTION MODE TECHNIQUES 审中-公开
标题翻译：使用有效的导电模式技术建模皮肤的影响
公开(公告)号：WO2008137774A3
公开(公告)日：2009-12-30
申请号：PCT/US2008062547
申请日：2008-05-02
申请人： MENTOR GRAPHICS CORP , SUAYA ROBERTO , ORTIZ SALVADOR
发明人： SUAYA ROBERTO , ORTIZ SALVADOR
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78
摘要： Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrand's for calculating the matrix elements into simplified terms that are less computationally intensive than the integrand's and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media).
摘要翻译：这里描述了用于提取用于电路设计的各种高频参数的方法的实施例。在一个示例性实施例中，接收指示电路设计中的导体的至少几何布局的电路设计信息和用于电路设计的期望的操作频率。定义表示在期望的操作频率下的导体中的电流的分布函数的导通模式。产生包括基于限定的导电模式的矩阵元素的导电模式矩阵。一个或多个矩阵元素的值是通过将被积函数分解为将矩阵元素计算为与被积函数计算密集程度较小并计算简化术语值的简化术语来计算的。一个或多个矩阵元素的值可以被存储（例如，在一个或多个计算机可读介质上）。

6. 发明申请

WO2003043057A3 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
公开(公告)号：WO2003043057A3
公开(公告)日：2003-05-22
申请号：PCT/US2002/036342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ESCOVAR, Rafael
发明人： SUAYA, Roberto , ESCOVAR, Rafael
IPC分类号： G06F17/50
摘要： A method of optimizing the propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed . The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires. The disclose method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedance at the junctions between the branches are substantially equal.

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